PROGRAM

1:00 pm – 4:00 pm | Price Center East Ballroom

Tutorial

Chair: Jishen Zhao

Caches for the Persistent Memory and Flash Era

Irfan Ahmad (CachePhysics) and Ymir Vigfusson (Emory University)

Slides:  Latest version

6:00 pm – 9:00 pm | Sheraton Hotel

7:45 am – 8:45 am | Price Center East Ballroom

Continental Breakfast

8:45 am – 9:00 am | Price Center East Ballroom

Opening Remarks

9:00 am – 10:00 am | Price Center East Ballroom

Keynote I

Flash Reliability in Production: The Importance of Measurement and Analysis in Improving System Reliability
Bianca Schroeder (University of Toronto);

Slides

Flash Reliability in Production: The Importance of Measurement and Analysis in Improving System Reliability

Bianca Schroeder (University of Toronto);

Speaker: Bianca Schroeder, University of Toronto

Slides

Abstract Solid-state drives (SSDs) based on NAND flash are making deep inroads into data centers as well as into the consumer market. As the amount of data stored on solid state drives keeps increasing, it is important to understand the reliability characteristics of these devices. For a long time, our knowledge about flash reliability was derived from controlled experiments in lab environments under synthetic workloads, often using methods for accelerated testing. In this talk, we present results from field studies on the failure behavior of flash devices in production environments subjected to real workloads and operating conditions. We also argue that collecting and analyzing field data is essential in building more reliable storage systems and present one specific case study demonstrating the use of machine learning techniques to reduce data loss in storage systems.

Speaker bio Bianca is an associate professor and Canada Research Chair in the Computer Science Department at the University of Toronto. She is also currently serving as associate department chair in Computer and Mathematical Sciences Department at the University of Toronto, Scarborough. Before joining UofT, she spent 2 years as a post-doc at Carnegie Mellon University working with Garth Gibson. She received her doctorate from the Computer Science Department at Carnegie Mellon University under the direction of Mor Harchol-Balter. She is an Alfred P. Sloan Research Fellow, the recipient of the Outstanding Young Canadian Computer Science Prize of the Canadian Association for Computer Science, an Ontario Early Researcher Award, an NSERC Accelerator Award, a two-time winner of the IBM PhD fellowship and her work has won four best paper awards and one best presentation award. She has co-chaired the TPCs of Usenix FAST'14, ACM Sigmetrics'14 and IEEE NAS'11. She is also a member of the Usenix FAST conference's steering committee and an associate editor for IEEE TDSC. Her work on storage reliability and her work on DRAM reliability have been featured in articles at a number of news sites, including Computerworld, Wired, Slashdot, PCWorld, StorageMojo and eWEEK.

10:00 am – 10:30 am

Break

10:30 am – 12:30 pm | Price Center East Ballroom

Session 1: Memorable Paper Award Finalists I

Chair: John (Jack) Sampson

Strata: A Cross Media File System
Youngjin Kwon (UT Austin); Henrique Fingler (UT Austin); Tyler Hunt (UT Austin); Simon Peter (UT Austin); Emmett Witchel (UT Austin); Thomas Anderson (University of Washington);

Extended abstract

Slides

Strata: A Cross Media File System

Youngjin Kwon (UT Austin); Henrique Fingler (UT Austin); Tyler Hunt (UT Austin); Simon Peter (UT Austin); Emmett Witchel (UT Austin); Thomas Anderson (University of Washington);

Speaker: Youngjin Kwon, The University of Texas at Austin

Extended abstract

Slides

Abstract Current hardware and application storage trends put immense pressure on the operating system's storage subsystem. On the hardware side, the market for storage devices has diversified to a multi-layer storage topology spanning multiple orders of magnitude in cost and performance. Above the file system, applications increasingly need to process small, random IO on vast data sets with low latency, high throughput, and simple crash consistency. File systems designed for a single storage layer cannot support all of these demands together. We present Strata, a cross-media file system that leverages the strengths of one storage media to compensate for weaknesses of another. In doing so, Strata provides performance, capacity, and a simple, synchronous IO model all at once, while having a simpler design than that of file systems constrained by a single storage device. At its heart, Strata uses a log-structured approach with a novel split of responsibilities among user mode, kernel, and storage layers that separates the concerns of scalable, high-performance persistence from storage layer management. We quantify the performance benefits of strata using a 3-layer storage hierarchy of emulated NVM, a flash-based SSD, and a high-density HDD. Strata has 20-30\% better latency and throughput, across several unmodified applications, compared to file systems purpose-built for each layer, while providing synchronous and unified access to the entire storage hierarchy. Finally, Strata achieves up to 2.8\times× better throughput than a block-based 2-layer cache provided by Linux's logical volume manager.

Speaker bio Youngjin Kwon is a Ph.D. student in The University of Texas at Austin, working with Prof. Emmett Witchel and Prof. Simon Peter. His research interests primarily lie in operating systems, including file systems, emerging storage and memory technologies, systems support for security, and virtualization

ReFlex: Remote Flash == Local Flash
Ana Klimovic (Stanford University); Heiner Litz (UC Santa Cruz, Google); Christos Kozyrakis (Stanford University);

Extended abstract

Slides

ReFlex: Remote Flash == Local Flash

Ana Klimovic (Stanford University); Heiner Litz (UC Santa Cruz, Google); Christos Kozyrakis (Stanford University);

Speaker: Ana Klimovic, Stanford University

Extended abstract

Slides

Abstract Remote access to NVMe Flash enables flexible scaling and high utilization of Flash capacity and IOPS within a datacenter. However, existing systems for remote Flash access either introduce significant performance overheads or fail to isolate the multiple remote clients sharing each Flash device. We present ReFlex, a software-based system for remote Flash access that provides nearly identical performance to accessing local Flash. ReFlex uses a dataplane kernel to closely integrate networking and storage processing to achieve low latency and high throughput at low resource requirements. Specifically, ReFlex can serve up to 850K IOPS per core over TCP/IP networking, while adding 21$\mu$s over direct access to local Flash. ReFlex uses a QoS scheduler that can enforce tail latency and throughput service-level objectives (SLOs) for thousands of remote clients. We show that ReFlex allows applications to use remote Flash while maintaining their original performance with local Flash. ReFlex was published in the proceedings of ASPLOS 2017. ReFlex is open-source software. The code is available at https://github.com/stanford-mast/reflex.

Speaker bio Ana Klimovic is a Ph.D. student at Stanford University, advised by Professor Christos Kozyrakis. Her research focuses on storage architectures and resource management for large-scale datacenters. Ana earned her M.S. in Electrical Engineering at Stanford and received her undergraduate degree in Engineering Science at the University of Toronto. She has interned at Facebook and Microsoft Research during her graduate studies. Ana is a Microsoft Research Ph.D. Fellow, Stanford Graduate Fellow and Accel Innovation Scholar.

LightNVM: The Linux Open-Channel SSD Subsystem
Matias Bjørling (CNEX Labs); Javier Gonzalez (CNEX Labs); Philippe Bonnet (IT University of Copenhagen);

Extended abstract

Slides

LightNVM: The Linux Open-Channel SSD Subsystem

Matias Bjørling (CNEX Labs); Javier Gonzalez (CNEX Labs); Philippe Bonnet (IT University of Copenhagen);

Speaker: Matias Bjørling, IT University of Copenhagen

Extended abstract

Slides

Abstract In our FAST’17 paper, we describe our experience build- ing LightNVM, the Open-Channel SSD subsystem in the Linux kernel. LightNVM is the first open, generic subsys- tem for Open-Channel SSDs and host-based SSD manage- ment. We make four contributions. First, we describe the characteristics of open-channel SSD management. We iden- tify the constraints linked to exposing SSD internals, discuss the associated trade-offs and lessons learned from the storage industry. Second, we introduce the Physical Page Address (PPA) I/O interface, an interface for Open-Channel SSDs, that defines a hierarchical address space together with control and vectored data commands. Third, we present LightNVM, the Linux subsystem that we designed and implemented for open- channel SSD management. It provides an interface where application-specific abstractions, denoted as targets, can be im- plemented. We provide a host-based Flash Translation Layer, called pblk, that exposes open-channel SSDs as traditional block I/O devices. Finally, we demonstrate the effectiveness of LightNVM on top of a first generation open-channel SSD. Our results are the first measurements of an open-channel SSD that exposes the physical page address I/O interface. We compare against state-of-the-art block I/O SSD and evaluate performance overheads when running synthetic, file system, and database system-based workloads. Our results show that LightNVM achieves high performance and can be tuned to control I/O latency variability.

Speaker bio Matias Bjorling is the author of the Open-Channel SSD specification and maintainer of the Open-Channel SSD subsystem (lightnvm) in the Linux kernel. Before joining the industry, he obtained a Ph.D. in operating systems, and non-volatile storage by doing performance characterization of flash-based SSDs, working on the Linux kernel blk-mq block layer, and its associated device drivers, while also laying the groundwork for the LightNVM subsystem.

NOVA-Fortis: A Fault-Tolerant Non-Volatile Main Memory File System
Jian Xu (UC San Diego); Lu Zhang (UC San Diego); Amirsaman Memaripour (UC San Diego); Akshatha Gangadharaiah (UC San Diego); Amit Borase (UC San Diego); Tamires Brito Da Silva (UC San Diego); Andy Rudoff (Intel); Steven Swanson (UC San Diego);

Extended abstract

Slides

NOVA-Fortis: A Fault-Tolerant Non-Volatile Main Memory File System

Jian Xu (UC San Diego); Lu Zhang (UC San Diego); Amirsaman Memaripour (UC San Diego); Akshatha Gangadharaiah (UC San Diego); Amit Borase (UC San Diego); Tamires Brito Da Silva (UC San Diego); Andy Rudoff (Intel); Steven Swanson (UC San Diego);

Speaker: Lu Zhang, UC San Diego

Extended abstract

Slides

Abstract Emerging fast, persistent memories will enable systems that combine conventional DRAM with large amounts of nonvolatile main memory (NVMM) and provide huge increases in storage performance. Fully realizing this potential requires fundamental changes in how system software manages, protects, and provides access to data that resides in NVMM. We address these needs by describing an NVMM-optimized file system called NOVA-Fortis that is both fast and resilient in the face of corruption due to media errors and software bugs. We identify and propose solutions for the unique challenges in adding fault tolerance to an NVMM file system, adapt state-of-the-art reliability techniques to an NVMM file system, and quantify the performance and storage overheads of these techniques.

Speaker bio Lu Zhang is a PhD student in the Non-Volatile Systems Lab (NVSL) of UC San Diego. He is interested in computer architecture and system software research, in particular the memory subsystem. Currently he is focusing on building fault-tolerant file systems and user-space programming libraries for software using persistent memory (PMEM). His previous research also includes hardware accelerators and associated driver software.

Architectural Support for Atomic Durability in Non-Volatile Memory
Arpit Joshi (University of Edinburgh); Vijay Nagarajan (University of Edinburgh); Stratis Viglas (University of Edinburgh); Marcelo Cintra (Intel);

Extended abstract

Architectural Support for Atomic Durability in Non-Volatile Memory

Arpit Joshi (University of Edinburgh); Vijay Nagarajan (University of Edinburgh); Stratis Viglas (University of Edinburgh); Marcelo Cintra (Intel);

Speaker: Arpit Joshi, University of Edinburgh

Extended abstract

Abstract Non-volatile memory (NVM) is emerging as a fast byte-addressable alternative for storing persistent data. Ensuring atomic durability in NVM requires logging. Existing techniques have proposed software logging either by using streaming stores for an undo log; or, by relying on the combination of clflush and mfence for a redo log. These techniques are suboptimal because they waste precious execution cycles to implement logging, which is fundamentally a data movement operation. We propose ATOM, a hardware log manager based on undo logging that performs the logging operation out of the critical path. We present the design principles behind ATOM and two techniques to optimize its performance. Our results show that ATOM achieves an improvement of 27% for micro-benchmarks and 60% for TPC-C over a baseline undo log design.

Speaker bio Arpit Joshi is a Research Associate in the School of Informatics at The University of Edinburgh. Prior to joining The University of Edinburgh, he spent more than two years working on the Xeon and Xeon-D family of processors at Intel. He also has a Masters degree from IIT Madras in India. His work focuses on efficient memory system design for emerging memory technologies and scale-out architectures.

Memory Management Techniques for Large-Scale Persistent-Main-Memory Systems
Ismail Oukid (SAP SE); Daniel Booss (SAP SE); Adrien Lespinasse (Independant); Wolfgang Lehner (TU Dresden); Thomas Willhalm (Intel Deutschland GmbH); Grégoire Gomes (Grenoble INP);

Extended abstract

Slides

Memory Management Techniques for Large-Scale Persistent-Main-Memory Systems

Ismail Oukid (SAP SE); Daniel Booss (SAP SE); Adrien Lespinasse (Independant); Wolfgang Lehner (TU Dresden); Thomas Willhalm (Intel Deutschland GmbH); Grégoire Gomes (Grenoble INP);

Speaker: Ismail Oukid, SAP SE

Extended abstract

Slides

Abstract Storage-Class Memory (SCM) is a novel class of memory technologies that promise to revolutionize database architectures. SCM is byte-addressable and exhibits latencies similar to those of DRAM, while being non-volatile. Hence, SCM could replace both main memory and storage, enabling a novel single-level database architecture without the traditional I/O bottleneck. Fail-safe persistent SCM allocation can be considered conditio sine qua non for enabling this novel architecture paradigm for database management systems. In this presentation, we present PAllocator, a fail-safe persistent SCM allocator whose design emphasizes high concurrency and capacity scalability. Contrary to previous works, PAllocator thoroughly addresses the important challenge of persistent memory fragmentation by implementing an efficient defragmentation algorithm. We show that PAllocator outperforms state-of-the-art persistent allocators by up to one order of magnitude, both in operation throughput and recovery time, and enables up to 2.39x higher operation throughput on a persistent B-Tree.

Speaker bio Ismail Oukid is a database researcher and developer at SAP SE. His research focuses on identifying and leveraging opportunities brought by new hardware advancements in data management systems. He received a PhD in Computer Science from TU Dresden in 2017. During his PhD thesis, he worked closely with SAP SE and Intel on revisiting the architectural principles of database systems in light of emerging Storage-Class Memories (SCM), which led him to design a novel single-level transactional storage engine, called SOFORT. Through his work, he gained in-depth insights into the challenges of SCM and investigated data structure design, memory management techniques, transaction concurrency control, and fail-safety testing techniques for SCM. He received an Engineering degree in Computer Science from the Grenoble Institute of Technology (Grenoble INP - Ensimag) in 2013.

12:30 pm – 2:00 pm | Price Center West Ballroom

Lunch and Poster Session

2:00 pm-4:00 pm | Price Center East Ballroom

Session 2: Memorable Paper Award Finalists II

Chair: Idan Alrod

A Three-Stage Approach for Designing Non-Binary Spatially-Coupled Codes for Flash Memories
Ahmed Hareedy (UCLA); Homa Esfahanizadeh (UCLA); Lara Dolecek (UCLA);

Extended abstract

Slides

A Three-Stage Approach for Designing Non-Binary Spatially-Coupled Codes for Flash Memories

Ahmed Hareedy (UCLA); Homa Esfahanizadeh (UCLA); Lara Dolecek (UCLA);

Speaker: Ahmed Hareedy, University of California, Los Angeles (UCLA)

Extended abstract

Slides

Abstract Modern dense Flash memory devices operate at very low error rates, which require powerful error correcting coding techniques. Here, our focus is on spatially-coupled (SC) codes. We present a three-stage approach for the design of high performance non-binary SC (NB-SC) codes optimized for practical Flash channels; we aim at minimizing the number of detrimental general absorbing sets of type two in the graph of the designed NB-SC code. Simulation results demonstrate the effectiveness of the NB-SC codes designed using our approach.

Speaker bio Ahmed Hareedy is a Ph.D. candidate in the Electrical and Computer Engineering Department at the University of California, Los Angeles (UCLA). He received his B.S. and M.S. degrees in Electronics and Communications Engineering from Cairo University in 2006 and 2011, respectively. His research interests include broadly applying coding/information theoretic concepts and techniques to solve problems associated with modern practical systems, e.g., data-hungry systems. Ahmed has industry experience as he worked with Mentor Graphics Corporation between 2006 and 2014. He worked as an error correcting codes architect with Intel Corporation in the summer of 2015 and the summer of 2017. Ahmed's B.S. group graduation project won the first prize at the IEEE Egyptian Engineering Day (EED), 2006. He is a recipient of the best paper award from the IEEE Global Communications Conference (GLOBECOM), 2015 (Selected Areas in Communications, Data Storage Track). In 2017, he was one of only four Ph.D. candidates in the Electrical Engineering Department at UCLA to win the Dissertation Year Fellowship (DYF). In the same year, he won the 2016-2017 Electrical Engineering Henry Samueli Excellence in Teaching Award for teaching Probability and Statistics (131A) at UCLA.

Syndrome-Coupled Rate-Compatible Error-Correcting Codes for Flash Memories
Pengfei Huang (UCSD); Yi Liu (UCSD); Xiaojie Zhang (CNEX Labs); Paul H. Siegel (UCSD); Erich F. Haratsch (Seagate Technology);

Extended abstract

Slides

Syndrome-Coupled Rate-Compatible Error-Correcting Codes for Flash Memories

Pengfei Huang (UCSD); Yi Liu (UCSD); Xiaojie Zhang (CNEX Labs); Paul H. Siegel (UCSD); Erich F. Haratsch (Seagate Technology);

Speaker: Pengfei Huang, CMRR, UCSD

Extended abstract

Slides

Abstract In this work, we propose a general framework for constructing rate-compatible ECCs based on cosets and syndromes of a set of nested linear codes. We evaluate our construction from two points of view. From a combinatorial perspective, we show that we can construct rate-compatible codes with increasing minimum distances. From a probabilistic point of view, we also prove that we are able to construct capacity-achieving rate-compatible codes. Performance of two-level rate-compatible codes is evaluated for a multilevel cell (MLC) flash memory.

Speaker bio Pengfei Huang received the B.E. degree in Electrical Engineering from Zhejiang University, Hangzhou, China, in 2010 and the M.S. degree in Electrical Engineering from Shanghai Jiao Tong University, Shanghai, China, in 2013. He is currently a Ph.D. student in the ECE department at UCSD and is working in Prof. Siegel’s STAR group. He is interested in wireless communications and storage systems. His current research focuses on advanced coding theory and distributed storage systems.

Accelerating Multiplication and Parallelizing Operations in Non-Volatile Memory
Mohsen Imani (University of California, San Diego); Saransh Gupta (University of California, San Diego); Tajana Rosing (University of California, San Diego);

Extended abstract

Slides

Accelerating Multiplication and Parallelizing Operations in Non-Volatile Memory

Mohsen Imani (University of California, San Diego); Saransh Gupta (University of California, San Diego); Tajana Rosing (University of California, San Diego);

Speaker: Saransh Gupta, University of California, San Diego

Extended abstract

Slides

Abstract Recent years have witnessed a rapid growth in the domain of Internet of Things (IoT). This network of billions of devices generates and exchanges huge amount of data. The limited cache capacity and memory bandwidth make transferring and processing such data on traditional CPUs and GPUs highly inefficient, both in terms of energy consumption and delay. However, many IoT applications are statistical at heart and can accept a part of inaccuracy in their computation. This enables the designers to reduce complexity of processing by approximating the results for a desired accuracy. In this paper, we propose an ultra-efficient approximate processing in-memory architecture, called APIM, which exploits the analog characteristics of non-volatile memories to support addition and multiplication inside the crossbar memory, while storing the data. The proposed design eliminates the overhead involved in transferring data to processor by virtually bringing the processor inside memory. APIM dynamically configures the precision of computation for each application in order to tune the level of accuracy during runtime. Our experimental evaluation running six general OpenCL applications shows that the proposed design achieves up to 20x performance improvement and provides 480x improvement in energy-delay product, ensuring acceptable quality of service. In exact mode, it achieves 28x energy savings and 4.8x speed up compared to the state-of-the-art GPU cores.

Speaker bio Saransh is a Masters student in the Electrical and Computer Engineering Department at the University of California, San Diego. He is a member of the System Energy Efficiency Lab (SEELab). His research interests include application of non-volatile memories focused towards in-memory computing.

Order-Optimal Permutation Codes in the Generalized Cayley Metric
Siyi Yang (University of California, Los Angeles); Clayton Schoeny (University of California, Los Angeles); Lara Dolecek (University of California, Los Angeles);

Extended abstract

Slides

Order-Optimal Permutation Codes in the Generalized Cayley Metric

Siyi Yang (University of California, Los Angeles); Clayton Schoeny (University of California, Los Angeles); Lara Dolecek (University of California, Los Angeles);

Speaker: Siyi Yang, UCLA

Extended abstract

Slides

Abstract Permutation codes have recently garnered substantial research interest due to their potential in flash memories. We study the theoretical bounds and the constructions of permutation codes in the generalized Cayley metric. The generalized Cayley metric captures the number of generalized transposition errors in a permutation, and subsumes previously studied error types, including transpositions and translocations, without imposing restrictions on the lengths and positions of the translocated segments. Relying on the breakpoint analysis proposed by Chee and Vu, we propose a coding scheme that is order-optimal.

Speaker bio Siyi Yang is a Ph.D. student in the Electrical and Computer Engineering Department at the University of California, Los Angeles (UCLA). She received her B.S. degree in Electrical Engineering from Tsinghua University in 2016. She also did her summer intern at Columbia University in 2015. Siyi is interested in coding theory and information theory, especially the theoretical part. She won the Scholarship of Academic Excellence from Tsinghua University in 2015. She was also a recipient of the departmental fellowship at UCLA in 2016. Before that, she won the 1st and 2nd place in the Chinese Girls Mathematical Olympiad in 2010 and 2011, respectively, and was elected to the Chinese National Mathematical Training Team in 2011.

Speeding Up Crossbar Resistive Memory by Exploiting In-memory Data Patterns
Wen Wen (University of Pittsburgh); Lei Zhao (University of Pittsburgh); Youtao Zhang (University of Pittsburgh); Jun Yang (University of Pittsburgh);

Extended abstract

Slides

Speeding Up Crossbar Resistive Memory by Exploiting In-memory Data Patterns

Wen Wen (University of Pittsburgh); Lei Zhao (University of Pittsburgh); Youtao Zhang (University of Pittsburgh); Jun Yang (University of Pittsburgh);

Speaker: Wen Wen, University of Pittsburgh

Extended abstract

Slides

Abstract Resistive Memory (ReRAM), when adopting crossbar architecture, has the smallest 4F$^2$ planar cell size, which is ideal for constructing dense memory with large capacity. However, crossbar cell structure suffers from large sneak leakage and IR drop on long wires. To ensure operation reliability, ReRAM writes, in particular, RESET operations, conservatively use the worst-case access latency of all cells in ReRAM arrays, which leads to significant performance degradation and dynamic energy waste. In this paper, we study the correlation between the RESET latency and the number of cells in low resistant state (LRS) along bitlines, and propose to dynamically speed up ReRAM RESET operations for the rows that have small numbers of LRS cells. We leverage the intrinsic in-memory processing capability of ReRAM crossbar and propose a low overhead runtime profiler that effectively tracks the data patterns in different bitlines. To achieve further RESET latency reduction, we employ data compression and row address dependent data layout to reduce LRS cells on bitlines. To the best of our knowledge, this paper is the first architectural innovation that exploits the bitline data patterns, e.g., the percentage of LRS cells, to speed up RESET operations in ReRAM crossbars. The experimental results show that, on average, our design improves system performance by 20.5% and 14.2%, and reduces memory dynamic energy by 15.7% and 7.6%, compared to the baseline and the state-of-the-art crossbar design.

Speaker bio Wen Wen is a PhD student in the Department of Electrical & Computer Engineering at the University of Pittsburgh. His advisor is Prof. Jun Yang, and he is also co-advised by Prof. Youtao Zhang from the Department of Computer Science. His current research interests primarily include computer architecture, emerging non-volatile memory technologies and GPU. He received the B.S. and M.S. degrees in Electronic Engineering from Southeast University, China in 2011 and 2014 respectively. He is now actively seeking for internship opportunities.

Optimal Data Shaping Code Design
Yi Liu (Electrical and Computer Engineering Dept., UCSD); Pengfei Huang (Electrical and Computer Engineering Dept., UCSD); Alexander W. Bergman (Electrical and Computer Engineering Dept., UCSD); Paul H. Siegel (Electrical and Computer Engineering Dept., UCSD);

Extended abstract

Slides

Optimal Data Shaping Code Design

Yi Liu (Electrical and Computer Engineering Dept., UCSD); Pengfei Huang (Electrical and Computer Engineering Dept., UCSD); Alexander W. Bergman (Electrical and Computer Engineering Dept., UCSD); Paul H. Siegel (Electrical and Computer Engineering Dept., UCSD);

Speaker: Yi Liu, Center for Memory and Recording Research (CMRR), UCSD

Extended abstract

Slides

Abstract Data shaping codes are designed to increase the lifetime of flash memory devices. In previous work, a general class of shaping codes was defined, subsuming the definitions of endurance codes and direct shaping codes. The minimum average cost per code symbol for a given expansion factor was characterized, and a separation theorem was proved, showing that optimal data shaping can be achieved by the concatenation of optimal lossless compression with optimal endurance coding. The expansion factor that minimizes the total cost, i.e., the average cost per input symbol, was also analyzed. Lifetime gains from the application of an MLC direct shaping code were demonstrated experimentally. In this paper, we address the construction of optimal shaping codes. Experimental results show a significant increase in device lifetime when the resulting codes are applied to English-language and Chinese-language works, providing total data capacity greater than that achieved by data compression alone.

Speaker bio Yi Liu received the B.E. degree in Physics from Peking University, Beijing, China, in 2014. He is currently a Ph, D, student in the ECE department at UCSD. His current research focuses on shaping codes and flash memory.

4:00 pm-4:20 pm

Break

4:20 pm – 5:00 pm | Price Center West Ballroom

Session 4: NVM and IOT

Chair: Xinmiao Zhang

Incidental Computing on IoT Nonvolatile Processors
Kaisheng Ma (psu); Xueqing Li (psu); Jinyang Li (thu); Yongpan Liu (thu); Yuan Xie (ucsb); Jack Sampson (psu); Mahmut Taylan Kandemir (psu); Vijaykrishnan Narayanan (psu);

Extended abstract

Incidental Computing on IoT Nonvolatile Processors

Kaisheng Ma (psu); Xueqing Li (psu); Jinyang Li (thu); Yongpan Liu (thu); Yuan Xie (ucsb); Jack Sampson (psu); Mahmut Taylan Kandemir (psu); Vijaykrishnan Narayanan (psu);

Speaker: Jack Sampson, Pennsylvania State University

Extended abstract

Abstract Batteryless IoT devices powered through energy harvesting face a fundamental imbalance between the potential volume of collected data and the amount of energy available for processing that data locally. However, many such devices perform similar operations across each new input record, which provides opportunities for mining the potential information in buffered historical data, at potentially lower effort, while processing new data rather than abandoning old inputs due to limited computational energy. We call this approach \textbf{incidental computing}, and highlight synergies between this approach and approximation techniques when deployed on a non-volatile processor platform (NVP). In addition to incidental computations, the backup and restore operations in an incidental NVP provide approximation opportunities and optimizations that are unique to NVPs. We propose a variety of incidental approximation approaches suited to NVPs, with a focus on approximate backup and restore, and approximate recomputation in the face of power interruptions. We perform RTL level evaluation for many frequently used workloads. We show that these incidental techniques provide an average of 4.2X more forward progress than precise NVP execution.

Speaker bio John (Jack) Sampson is an Assistant Professor in the Computer Science and Engineering department at Penn State. He joined the Penn State faculty in 2013 after working as a postdoctoral scholar at UCSD, where he received his PhD in 2010. His primary research interests lie broadly in the area of computer architecture, with specific interests in low-power and energy-efficient designs enabled by emerging logic and memory technologies. A key focus of his recent work has been the investigation of how distributed, on-chip non-volatile memory elements enable “non-volatile processors” that can provide reliable execution with unreliable power income. His work on energy-harvesting non-volatile processors has been recognized with two best paper awards (HPCA 2015, ASP-DAC 2017) and an IEEE Micro Top Picks selection.

Peripheral State Persistence and Interrupt Management For Transiently Powered Systems
Gautier Berthou (Univ. Lyon, INSA-Lyon, Inria); Tristan Delizy (Univ. Lyon, INSA-Lyon, Inria); Kevin Marquet (Univ. Lyon, INSA-Lyon, Inria); Tanguy Risset (Univ. Lyon, INSA-Lyon, Inria); Guillaume Salagnac (Univ. Lyon, INSA-Lyon, Inria);

Extended abstract

Slides

Peripheral State Persistence and Interrupt Management For Transiently Powered Systems

Gautier Berthou (Univ. Lyon, INSA-Lyon, Inria); Tristan Delizy (Univ. Lyon, INSA-Lyon, Inria); Kevin Marquet (Univ. Lyon, INSA-Lyon, Inria); Tanguy Risset (Univ. Lyon, INSA-Lyon, Inria); Guillaume Salagnac (Univ. Lyon, INSA-Lyon, Inria);

Speaker: Gautier Berthou, Univ Lyon, Inria, INSA Lyon, CITI

Extended abstract

Slides

Abstract Recently has emerged the concept of transiently powered systems powered by harvesting power and being able to retain information between power failures using non-volatile RAM. While existing solutions focus on purely computing systems, this article presents Sytare, a software layer designed to allow the use of non-trivial peripherals such as timers, serial interface or radio devices in transiently powered systems.

Speaker bio Gautier holds a Master degree from KTH Royal Institute of Technology as well as a Master degree from engineering school INSA Lyon. After one year working as engineer on a research project dedicated to NVRAM management in transiantly-powered systems, he has just started working as PhD student in the Socrate team of INRIA/CITI lab.

6:00 pm – 9:00 pm

8:00 am – 9:00 am | Price Center East Ballroom

Continental Breakfast

9:00 am – 10:00 am | Price Center East Ballroom

Keynote II

Persistent Memory: from Samples to Mainstream Adoption
Amit Golander (NetApp);

Slides

Persistent Memory: from Samples to Mainstream Adoption

Amit Golander (NetApp);

Speaker: Amit Golandar, NetApp

Slides

Abstract Persistent Memory (PM) is near-memory speed storage that provides byte-addressable granular access. PM disruption extends beyond the hardware itself and is revolutionizing storage software and operating system I/O stack. Moreover, it may even shift traditional responsibilities from the storage to the application administrator. In this talk, we will survey the software approaches for leveraging PM, focusing on the approach Plexistor (acquired by NetApp) chose and why. We will describe some of steps NetApp is taking to usher PM into mainstream adoption, such as offsetting PM costs using auto-tiering; providing advanced data protection schemes; and increasing portability by contributing a new kernel-to-user space file system bridge called ZUFS.

Speaker bio Dr. Amit Golander is a Technical Director at NetApp, where he leads the development of the Plexistor persistent memory based software. Amit is a technology leadership expert with Product and BD skills forged at Plexistor, Tonian and IBM. Amit has a rich R&D background, leading global software and hardware technical teams since 2000 and composing over 60 papers and patents. Amit holds a PhD in Computer Architecture and diverse work experience in Storage, Servers and Networking.

10:00 am – 10:10 am

10:10 am – 10:40 am

Break

10:40 am – 12:00 pm | Price Center East Ballroom

10:40 am – 12:00 pm | Price Center West Ballroom

Session 5: Near Data Processing/Datacenter

Chair:Ameen Akel

Visual Object Recognition Accelerator Based on Approximate In-Memory Processing
Yeseong Kim (University of California San Diego); Mohsen Imani (University of California San Diego); Tajana Rosing (University of California San Diego);

Extended abstract

Slides

Visual Object Recognition Accelerator Based on Approximate In-Memory Processing

Yeseong Kim (University of California San Diego); Mohsen Imani (University of California San Diego); Tajana Rosing (University of California San Diego);

Speaker: Mohsen Imani, UC San Diego

Extended abstract

Slides

Abstract Machine learning has been widely investigated as an autonomous solution which performs diverse classification tasks, e.g., voice recognition and visual object detection. However, running these tasks in conventional computer architectures requires high energy consumption due to large data movement and memory accesses. In this paper, we propose a novel accelerator design, called CHOIR, which performs the classification tasks based on a co-designed boosting algorithm. Since CHOIR processes most classification tasks inside emerging non-volatile memory blocks, we can significantly mitigate computation overhead incurred by the enormous amount of data. In our evaluation conducted on circuit and device-level simulations, we show that the CHOIR successfully performs practical classification tasks with high accuracy, e.g., more than 96% for practical image recognition problems. In addition, our design significantly improves the performance and energy efficiency by up to 376x and 1896x, respectively, compared to the existing processor-based implementation

Speaker bio Mohsen Imani is a PhD candidate in the Department of Computer Science and Engineering (CSE) at the University of California, San Diego (UCSD). He is a member of System Energy Efficiency Lab (SeeLab). His research focuses on computer architecture, machine learning and brain-inspired computing.

Dynamic Near Data Processing Framework for SSDs
Gunjae Koo (University of Southern California); Kiran Kumar Matam (University of Southern California); Te I (North Carolina State University); H. V. Krishna Giri Narra (University of Southern California); Jing Li (University of California, San Diego); Hung-Wei Tseng (North Carolina State University); Steven Swanson (University of California, San Diego); Murali Annavaram (University of Southern California);

Extended abstract

Slides

Dynamic Near Data Processing Framework for SSDs

Gunjae Koo (University of Southern California); Kiran Kumar Matam (University of Southern California); Te I (North Carolina State University); H. V. Krishna Giri Narra (University of Southern California); Jing Li (University of California, San Diego); Hung-Wei Tseng (North Carolina State University); Steven Swanson (University of California, San Diego); Murali Annavaram (University of Southern California);

Speaker: Gunjae Koo, University of Southern California

Extended abstract

Slides

Abstract Modern data center solid state drives (SSDs) integrate multiple general-purpose embedded cores to manage flash translation layer, garbage collection, wear-leveling, and etc., to improve the performance and the reliability of SSDs. As the performance of these cores steadily improves there are opportunities to repurpose these cores to perform application driven computations on stored data, with the aim of reducing the communication between the host processor and the SSD. Reducing host-SSD bandwidth demand cuts down the I/O time which is a bottleneck for many applications operating on large data sets. However, the embedded core performance is still significantly lower than the host processor, as generally wimpy embedded cores are used within SSD for cost-effective reasons. So there is a trade-off between the computation overhead associated with near SSD processing and the reduction in communication overhead to the host system. In this work, we design a set of application programming interfaces (APIs) that can be used by the host application to offload a data-intensive task to the SSD processor. We describe how these APIs can be implemented by simple modifications to the existing Non-Volatile Memory Express (NVMe) command interface between the host and the SSD processor. We then quantify the computation versus communication tradeoffs for near storage computing using applications from two important domains, namely data analytics and data integration. Using a fully functional SSD evaluation platform we perform design space exploration of our proposed approach by varying the bandwidth and computation capabilities of the SSD processor. We evaluate static and dynamic approaches for dividing the work between the host and SSD processor, and show that our design may improve the performance by up to 20% when compared to processing at the host processor only, and 6X when compared to processing at the SSD processor only.

Speaker bio Gunjae Koo is a Ph.D. Candidate in the Department of Electrical Engineering at the University of Southern California (USC) working with Professor Murali Annavaram. His research interest is in computer architecture, memory systems, storage systems and accelerator design. His current research focuses on memory systems of parallel processors and near data processing on storage platforms. He earned his B.S. and M.S. degrees in Electrical and Computer Engineering at Seoul National University, South Korea. He worked for LG Electronics Digital TV and System IC laboratory as a senior research engineer involved in multiple research projects developing SoCs for storage devices and digital TVs. He also worked on high-performance memory controller for server architecture at Intel.

Distributed Shared Persistent Memory
Yizhou Shan (Purdue University); Shin-Yeh Tsai (Purdue University); Yiying Zhang (Purdue University);

Extended abstract

Distributed Shared Persistent Memory

Yizhou Shan (Purdue University); Shin-Yeh Tsai (Purdue University); Yiying Zhang (Purdue University);

Speaker: Yiying Zhang, Purdue University

Extended abstract

Abstract Next-generation non-volatile memories (NVMs) will provide byte addressability, persistence, high density, and DRAM-like performance. They have the potential to benefit many datacenter applications. However, most previous research on NVMs has focused on using them in a single machine environment. It is still unclear how to best utilize them in distributed, datacenter environments. We introduce Distributed Shared Persistent Memory (DSPM), a new framework for using persistent memories in distributed datacenter environments. DSPM provides a new abstraction that allows applications to both perform traditional memory load and store instructions and to name, share, and persist their data. We built Hotpot, a kernel-level DSPM system that provides low latency, transparent memory accesses, data persistence, data reliability, and high availability. The key ideas of Hotpot are to integrate distributed memory caching and data replication techniques and to exploit application hints. We implemented Hotpot in the Linux kernel and demonstrated its benefits by building a distributed graph engine on Hotpot and porting a NoSQL database to Hotpot. Our evaluation shows that Hotpot outperforms a recent distributed shared memory system by 1.3× to 3.2× and a recent distributed PM-based file system by 1.5× to 3.0×.

Speaker bio Yiying Zhang is an assistant professor in the School of Electrical and Computer Engineering at Purdue University. Her research interests span operating systems, distributed systems, datacenter networking, and computer architecture, with a recent focus on building network, software, and hardware systems for resource disaggregation. She leads WukLab, a systems research lab aiming to build next-generation datacenter systems at Purdue. Yiying received her Ph.D. from the Department of Computer Sciences at the University of Wisconsin-Madison and worked as a postdoctoral scholar at the University of California, San Diego before joining Purdue.

Heterogeneous Memory Management in Datacenter
Sudarsun Kannan (University of Wisconsin-Madison); Ada Gavrilovska (Georgia Institute of Technology); Vishal Gupta (VMWare); Karsten Schwan ();

Extended abstract

Slides

Heterogeneous Memory Management in Datacenter

Sudarsun Kannan (University of Wisconsin-Madison); Ada Gavrilovska (Georgia Institute of Technology); Vishal Gupta (VMWare); Karsten Schwan ();

Speaker: Sudarsun Kannan, University of Wisconsin-Madison

Extended abstract

Slides

Abstract Heterogeneous memory management combined with server virtualization in data-centers is expected to increase the software and OS management complexity. State-of-the-art solutions for both virtualized and non-virtualized systems rely exclusively on the expensive page migrations techniques, limiting the benefits from heterogeneity. To address this, we design HeteroOS, a novel application-transparent OS-level solution that exposes memory heterogeneity to guest-OS for heterogeneity management in a virtualized system. Evaluation of HeteroOS with memory, storage, and network-intensive datacenter applications show up to 2x performance improvement compared to the state-of-the-art page migration techniques.

Speaker bio Sudarsun is a postdoctoral research associate at the University of Wisconsin-Madison, where he works on operating systems and storage research. His postdoctoral advisors are Prof. Andrea Arpaci-Dusseau and Prof. Remzi Arpaci-Dusseau. Sudarsun received a Ph.D. in Computer Science from Georgia Tech in 2016 under the guidance of the late Prof. Karsten Schwan and Prof. Ada Gavrilovska. Sudarsun's research focus is at the intersection of hardware and software, building operating systems and system software for next-generation memory and storage technologies. Sudarsun's research has appeared at premier operating systems and architecture venues including patents related to nonvolatile memory and resource management. In addition, he has taught several graduate and undergraduate-level courses, and he was nominated for the Georgia Tech-wide Outstanding Teaching Assistant Award.

Session 6: Coding Methods

Chair: Andrew Jiang

A Fresh Look at the Berlekamp-Massey Algorithm with Application to Low Power BCH decoding
Ishai Ilani (WDC);

Extended abstract

Slides

A Fresh Look at the Berlekamp-Massey Algorithm with Application to Low Power BCH decoding

Ishai Ilani (WDC);

Speaker: Ishai Ilani, Western Digital Corporation

Extended abstract

Slides

Abstract BCH codes are gaining renewed attention lately as new applications based on Storage Class Memories (SCM) and fast NAND require codes with multiple error correction capability, and low latency decoding. BCH are a natural choice for an Error Correcting Code (ECC) for such applications. The main challenge for high speed decoding of such codes is computing the Error Locator Polynomial (ELP). Two main algorithms used for this challenge are the extended Euclidean (eE) and the Berlekamp-Massey (BM) algorithms. Efficient architectures for implementing the BM algorithm, (by simultaneous computation of discrepancies and updates), for decoding the wider class of Reed Solomon (RS) and BCH codes result in equivalence between BM algorithms and eE algorithms, and in some cases BM algorithms may have properties which will make them more attractive. In this paper we focus our attention to the class of Primitive Narrow Sense BCH codes. In this case the efficient architectures become even more efficient, and the area and power requirements for implementing the BM algorithm reduce by 33%. Combining these results with computation of the BM algorithm in a low latency mode result in a very efficient low power and low latency algorithm. Also a closer look at the parity check matrix of a RS or BCH code reveals a natural way for introducing the ELP into the algorithm, and a close similarity between the BM and eE algorithms.

Speaker bio Ishai Ilani was born in Jerusalem, Israel, in 1957. He received the B.Sc., M.Sc. and Ph.D. degrees in mathematics from the Hebrew University, Jerusalem. From 1997-2000 he was a Researcher at ECI Telecom. From 2000 to 2007 he was Company Scientist at Actelis Networks. In both positions he was active in DSL Standard committees, (ITU-T, ANSI, ETSI). From 2012 he held a position of Principal Research Engineer at SanDisk Corporation, in Kfar Saba, Israel. Following the acquisition of SanDIsk by Western Digital, he is now a Senior Technologist at Western Digital Corporation.

Modified Generalized Integrated Interleaved Codes for Local Erasure Recovery
Xinmiao Zhang (The Ohio State University);

Extended abstract

Slides

Modified Generalized Integrated Interleaved Codes for Local Erasure Recovery

Xinmiao Zhang (The Ohio State University);

Speaker: Xinmiao Zhang, The Ohio State University

Extended abstract

Slides

Abstract Locally recoverable codes allow erasures to be corrected from a portion of codeword symbols and are essential to address the high reliability and performance requirements of hyper-scale distributed storage. Generalized integrated interleaved (GII) codes allocate parities shared by the interleaves, and require lower redundancy to achieve target reliability. However, all interleaves need to be read in order to make use of the shared parities. In this paper, GII codes are modified to improve the locality. Without sacrificing the erasure correction capability, the proposed scheme accesses much fewer interleaves when only a small number of extra erasures need to be recovered using the shared parities, which happens in most cases. As a result, the average locality is greatly improved. Compared to existing local erasure recovery schemes, the modified GII codes achieve a good tradeoff on locality and correction capability.

Speaker bio Xinmiao Zhang received her Ph.D. degree in Electrical Engineering from the University of Minnesota, Twin Cities. She was a Timothy E. and Allison L. Schroeder Assistant Professor 2005-2010 and Associate Professor 2010-2013 at Case Western Reserve University. She has been with Western Digital/ SanDisk 2013-2017, and joined The Ohio State University in 2017 as an Associate Professor. She also held visiting positions at the University of Washington, Seattle, 2011-2013 and Qualcomm in 2008. Dr. Zhang’s research spans the areas of VLSI architecture design, digital storage and communications, security, and signal processing. Prof. Zhang received an NSF CAREER Award in January 2009. She developed many architectures to improve the hardware efficiency of state-of-the-art error-correcting codes, including hard- and soft-decision BCH and Reed-Solomon codes, binary and non-binary low-density parity-check codes, and authored the book “VLSI Architectures for Modern Error-Correcting Codes” (CRC 2015). Prof. Zhang is a member of the IEEE Circuits and Systems for Communications (CASCOM), VLSI System Applications (VSA), Design and Implementation of Signal Processing Systems (DISPS), and Data Storage (DSTC) technical committees. She is also the Vice-Chair from Industry of the DSTC 2017-2018. She has served on the committees of many conferences, including ISCAS, ICASSP, GLOBECOM, GlobalSIP, SiPS, ICC, and NVMW, and will be the Chair of the Data Storage Track of ICC 2019. Prof. Zhang has been an associate editor for the IEEE Transactions on Circuits and Systems-I since 2010, and was a recipient of the Best Associate Editor Award in 2013.

On Sequential Locally Repairable Codes
Wentu Song (Singapore University of Technology and Design); Chau Yuen (Singapore University of Technology and Design); Kui Cai (Singapore University of Technology and Design); Kai Cai (University of Hong Kong); Guangyue Han (University of Hong Kong);

Extended abstract

Slides

On Sequential Locally Repairable Codes

Wentu Song (Singapore University of Technology and Design); Chau Yuen (Singapore University of Technology and Design); Kui Cai (Singapore University of Technology and Design); Kai Cai (University of Hong Kong); Guangyue Han (University of Hong Kong);

Speaker: Wentu Song, Singapore University of Technology and Design

Extended abstract

Slides

Abstract We consider the locally repairable codes (LRC), aiming at sequentially recovering multiple erasures. Specifically, we define the (n, k, r, t)-SLRC (Sequential Locally Repairable Codes) as an [n, k] linear code where any t' (t'<=t) erasures can be sequentially recovered, each by r (2 =< r < k) other code symbols. Here, sequential recovering means that the erased symbols are recovered one by one, and an already recovered symbol can be used to recover the remaining erased symbols. This important recovering method, in contrast with the extensively studied parallel recovering, is currently far from being thoroughly understood. In this paper, we first derive a tight upper bound on the code rate of the (n, k, r, t)-SLRC for t = 3 and r >= 2. We then propose two constructions of binary (n, k, r, t)-SLRCs for general r, t>=2 (Existing constructions only deal with t<=7 erasures). The first construction generalizes the method of direct product construction. The second construction is based on the resolvable configurations and yields SLRCs for any r>=2 and odd t>=3. For both constructions, the rates are optimal for t=2 and t=3, and are higher than most of the existing LRC families for arbitrary t>=4.

Speaker bio Wentu Song received the BS and MS degrees in Mathematics from Jilin University, China in 1998 and 2006, respectively, and the Ph.D. degree in Mathematics from Peking University in 2012, China. He is currently a Post Doc research fellow of Advanced Coding and Signal Processing Lab, Singapore University of Technology and Design, where he is working on coding theory, network coding and network distributed storage.

Codes for Correcting Tandem Repeats
Yeow Meng Chee (Nanyang Technological University); Johan Chrisnata (Nanyang Technological University); Han Mao Kiah (Nanyang Technological University); Tuan Thanh Nguyen (Nanyang Technological University);

Extended abstract

Slides

Codes for Correcting Tandem Repeats

Yeow Meng Chee (Nanyang Technological University); Johan Chrisnata (Nanyang Technological University); Han Mao Kiah (Nanyang Technological University); Tuan Thanh Nguyen (Nanyang Technological University);

Speaker: Johan Chrisnata, Nanyang Technological University

Extended abstract

Slides

Abstract Tandem duplication in DNA is the process of inserting a copy of a segment of DNA adjacent to the original position. Motivated by applications that store data in living organisms, Jain et al. (2016) proposed the study of codes that correct tandem duplications to improve the reliability of data storage. We investigate algorithms associated with the study of these codes. Two words are said to be ${\le}k$-confusable if there exists two sequences of tandem duplications of lengths at most $k$ such that the resulting words are equal. We demonstrate that the problem of deciding whether two words is ${\le}k$-confusable is linear-time solvable through a characterisation that can be checked efficiently for $k=3$. Using insights gained from the algorithm, we study the size of tandem-duplication codes. We improve the previous known upper bound and then construct codes with larger sizes as compared to the previous constructions. We determine the sizes of optimal tandem-duplication codes for lengths up to twenty, and develop recursive methods to construct tandem-duplication codes for all word lengths.

Speaker bio Johan Chrisnata received his Bachelor degree in mathematics from Nanyang Technological University (NTU), Singapore in 2015. Since then, he has been a Project Officer in NTU. His research interest includes Enumerative Combinatorics and Coding Theory.

12:00 pm – 1:40 pm | Price Center West Ballroom

Lunch / Poster Session

1:40 pm – 3:00 pm | Price Center West Ballroom

Session 8: Persistence (I)

Chair: Jian Huang

Boosting Persistence Parallelism in Memory Bus and RDMA Network
Xing Hu (UCSB); Matheus Ogleari (UCSC); Jishen Zhao (UCSD); Shuangchen Li (UCSB); Yuan Xie (UCSB);

Extended abstract

Boosting Persistence Parallelism in Memory Bus and RDMA Network

Xing Hu (UCSB); Matheus Ogleari (UCSC); Jishen Zhao (UCSD); Shuangchen Li (UCSB); Yuan Xie (UCSB);

Speaker: Xing Hu, University of Santa Barbara

Extended abstract

Abstract Emerging non-volatile memories (NVMs) incorporate the features of fast byte-addressability and data persistence, which are beneficial for data services, such as file systems and databases. To support data persistence, a persistent memory system requires ordering for write requests. We observe that the memory bus and the Remote Direct Memory Access (RDMA) network are severely under-utilized during the process of ensuring data persistence, because the \textbf{persistence parallelism} in the memory bus and the RDMA network is not fully leveraged during ordering. To address this problem, we propose an architecture design to exploit the persistence parallelism in the memory bus and the RDMA network. First, we utilize \textit{inter-thread persistence parallelism} for barrier epoch management with better bank-level parallelism (BLP). Second, we enable \textit{intra-thread persistence parallelism} with multiple barrier epochs inside one network packet, and propose a fine-grained memory persistence scheme through the network. %for the first time. With these features, our architecture is capable of efficiently supporting transaction-level persistence through RDMA network for file systems or NVM libraries. The experimental results show that our work can achieve 1.3$\times$ performance improvement for local applications and about 1.93$\times$ for remote applications serviced through the RDMA network.

Speaker bio I'm a postdoc working with Prof. Yuan Xie, in SEALab, Dept. of ECE, UCSB since 2017. I received Ph. D. degrees from Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS). After my graduation, I joined the Central Research Department of Huawei Technologies, working on the memory systems in data center architectures. My research interests include processing in memory, with emphasis on emerging NVM. (2) persistent memory system architecture design and optimization;

NVthreads: Practical Persistence for Multi-threaded Applications
Terry Hsu (Purdue University); Helge Brügner (TU Münchun); Indrajit Roy (Google Inc.); Kimberly Keeton (Hewlett Packard Labs); Patrick Eugster (Università della Svizzera italiana, Purdue University);

Extended abstract

Slides

NVthreads: Practical Persistence for Multi-threaded Applications

Terry Hsu (Purdue University); Helge Brügner (TU Münchun); Indrajit Roy (Google Inc.); Kimberly Keeton (Hewlett Packard Labs); Patrick Eugster (Università della Svizzera italiana, Purdue University);

Speaker: Terry Hsu, Purdue University

Extended abstract

Slides

Abstract Recently proposed frameworks for persistent programming provide multiple ways to directly manipulate data structures stored in non-volatile memory (NVM). Application developers can either rewrite their program to use durable transactions (NV-Heaps, Mnemosyne) or rely on the compiler and runtime system to infer failure atomic regions from locks (Atlas). These approaches track persistent data at a very fine granularity, such as at the level of individual store operations, and use cache flushes and write-ahead logging to correctly recover from failures. Unfortunately, the high overheads of tracking, logging, and managing volatile caches in these systems result in a huge overhead -- sometimes an order of magnitude slowdown between unmodified DRAM based applications and their crash tolerant versions. Certain systems propose hardware modifications to ameliorate the cost of cache flushes and ordering of NVM writes but do not work on today’s processors. Our goal is to provide a simple transition path for existing C/C++ programs to leverage non-volatile memory. We want to enable the use of NVM with few or no program modifications, and yet have good performance on today’s processors. Our key observation is that, for many applications, the high overheads of maintaining logs can be reduced substantially by using coarse- grained tracking, such as at the level of memory pages.

Speaker bio Terry is a PhD candidate in Computer Science at Purdue University. His research is concerned with the development of operating systems. Particular topics of interest include system security, memory safety, privilege separation, and software support for non-volatile memory.

Dalí: A Periodically Persistent Hash Map
Faisal Nawab (University of California, Santa Cruz); Joseph Izraelevitz (University of Rochester); Charles B. Morrey (); Dhruva Chakrabarti (); Michael L. Scott ();

Extended abstract

Dalí: A Periodically Persistent Hash Map

Faisal Nawab (University of California, Santa Cruz); Joseph Izraelevitz (University of Rochester); Charles B. Morrey (); Dhruva Chakrabarti (); Michael L. Scott ();

Speaker: Faisal Nawab, University of California, Santa Cruz

Extended abstract

Abstract Technology trends suggest that byte-addressable nonvolatile memory (NVM) will supplant many uses of DRAM over the coming decade, raising the prospect of inexpensive recovery from power failures and similar faults. Ensuring the consistency of persistent state remains nontrivial, however, in the presence of volatile caches; cached values can "leak" back to persistent memory in arbitrary order. To ensure consistency, existing persistent memory algorithms use expensive, explicit write-back instructions to force each value back to memory before performing a dependent write, thereby incurring significant run-time overhead. To reduce this overhead, we present a new design paradigm that we call periodic persistence. In a periodically persistent data structure, updates are made "in place," but can safely leak back to memory in any order, because only those updates that are known to be valid will be heeded during recovery. To guarantee forward progress, we periodically force a write-back of all dirty data in the cache, ensuring that all "sufficiently old" updates have indeed become persistent, at which point they become semantically visible to the recovery process. As an example of periodic persistence, we present a transactional hash map, Dalí, provably correct under buffered durable linearizability. Experiments with a prototype implementation suggest that periodic persistence can offer substantially better performance than either file-based or incrementally persistent (per-access write-back) alternatives.

Speaker bio Faisal Nawab is an assistant professor in the Computer Science department at UC Santa Cruz. His research lies at the intersection of Big Data management and distributed Cloud Computing systems. Specifically, he works on data management systems that accelerate and support data science and global connectivity especially in the domains of autonomous, mobile applications and the Internet of Things.

Continuous Checkpointing of HTM Transactions in NVM
Ellis Giles (Rice University); Kshitij Doshi (Intel Corporation); Peter Varman (Rice University);

Extended abstract

Continuous Checkpointing of HTM Transactions in NVM

Ellis Giles (Rice University); Kshitij Doshi (Intel Corporation); Peter Varman (Rice University);

Speaker: Ellis Giles, Rice University

Extended abstract

Abstract This paper addresses the challenges of coupling byte-addressable non-volatile memory (NVM) and hardware transaction memory (HTM) in high-performance transaction processing. We first show that HTM transactions can be ordered using existing processor instructions without any hardware changes. We exploit the ordering mechanism to design a novel persistence method that decouples HTM concurrency from back-end NVM operations. Failure atomicity is achieved using redo logging coupled with aliasing to guard against mistimed cache evictions. Our algorithm uses efficient lock-free mechanisms with bounded static memory requirements.

Speaker bio Ellis Giles is a Ph.D. candidate in ECE at Rice University. Before returning to Rice for graduate school, Ellis was the Enterprise Architect for ISS Mission Integration for NASA. He has worked at several startup companies that have licensed technology to Fortune 500 companies. Ellis is an Eagle Scout, holds several patents, and received the Ken Kennedy - Cray Fellowship.

3:00 pm – 3:20 pm

3:20 pm – 4:40 pm | Price Center West Ballroom

Session 10: Persistence (II)

Chair: Gunjae Koo

Efficient Durability for Lock-based Code
Swapnil Haria (University of Wisconsin-Madison); Pratyush Mahapatra (University of Wisconsin-Madison); Mark D. Hill (University of Wisconsin-Madison); Michael M. Swift (University of Wisconsin-Madison);

Extended abstract

Efficient Durability for Lock-based Code

Swapnil Haria (University of Wisconsin-Madison); Pratyush Mahapatra (University of Wisconsin-Madison); Mark D. Hill (University of Wisconsin-Madison); Michael M. Swift (University of Wisconsin-Madison);

Speaker: Swapnil Haria, University of Wisconsin-Madison

Extended abstract

Abstract Durable lock-based code is currently plagued by high flushing overheads (same as with persistent transactions) and expensive software tracking of synchronization history. In this work, we first show that the Hands-Off Persistence System (HOPS), originally designed for persistent transactions, has benefits for persistent lock-based code. Second, we show that HOPS can be extended to HOPS+ with hardware dependency tracking to replace expensive software tracking of SH. Our evaluation shows that HOPS+ improves the performance of durable lock-based code by 108% compared to existing x86-64 hardware and is 18% better than unmodified HOPS.

Speaker bio Swapnil is a 4th year PhD Student with Prof. Mark Hill and Prof. Michael Swift in the Multifacet group at UW Madison. Prior to joining UW-Madison, he completed his undergraduate studies from BITS, Pilani in India. He spent about two years working on the Denver CPU at NVIDIA, which motivated him to pursue research in architecture. His work focuses on redesigning memory systems to better fit heterogeneous compute and heterogeneous memory systems.

Logging in Persistent Memory: to Cache, or Not to Cache?
Mengjie Li (UCSC); Matheus Ogleari (UCSC); Jishen Zhao (UCSD);

Extended abstract

Slides

Logging in Persistent Memory: to Cache, or Not to Cache?

Mengjie Li (UCSC); Matheus Ogleari (UCSC); Jishen Zhao (UCSD);

Speaker: Matheus Ogleari, University of California, Santa Cruz

Extended abstract

Slides

Abstract Persistent memory is a new class of memory that functions as a hybrid of traditional storage systems and main memory. It combines the benefits of both the data persistence property of storage and the fast load/store interface of memory. In order to maintain data persistence in memory, a widely used mechanism is logging – in addition to updating the original data structures as in traditional memory systems, persistent memory systems also log the update. Most previous persistent memory studies suggest that log updates should bypass the cache hierarchy because the log is only used for system recovery and will not be reused during program execution. Caching the log only contaminates critical cache resources, leading to performance degradation. However, our study shows that current cache bypassing schemes (e.g., cache bypassing instructions and write-combining buffers) are sub-optimal for accommodating log writes. Making the log uncacheable can degrade persistent memory system performance worse than with cacheable logging. This presentation outlines our observations of the trade-offs between cacheable and uncacheable logging, based on our experimental results. We also analyze the reasons that lead to such trade-offs.

Speaker bio I am a fifth year PhD student in Computer Engineering Department at the University of California, Santa Cruz. I specialize in computer architecture and VLSI. My adviser is Professor Jishen Zhao. Currently, my work focuses on complexity-effective microarchitecture solutions for persistent memory systems. I am also affiliated with the Storage Systems Research Center. My research falls primarily in the area of computer architecture, with an emphasis on persistent memory systems, RTL design, and complexity-effective microarchitecture. I am also interested in electronics design automation and VLSI design. I received my Master or Science degree from the Department of Computer Engineering at University of California, Santa Cruz. I received my Bachelor of Science degree from the Department of Electrical and Computer Engineering at Cornell University. While at Cornell, I was involved in research into on-chip networks with Professor Chris Batten. I've had five different summer internships at Intel beginning in summer 2012. In 2012, I did pre-silicon validation for the power control unit of the Skylake server (Xeon) chip. In 2013 and 2014, I did pre-silicon validation for the cache coherency interface of the Knight's Landing (Xeon Phi) chip. In 2015, I did RTL design and unit-testing for the hardware performance monitor on the Knight's Hill (Xeon Phi) chip. I also had an internship at Huawei where I developed an adaptive prefetcher design.

Proteus: A Flexible and Fast Software Supported Hardware Logging approach for NVM
Seunghee Shin (North Carolina State University); Satish Kumar Tirukkovalluri (North Carolina State University); James Tuck (North Carolina State University); Yan Solihin (North Carolina State University);

Extended abstract

Slides

Proteus: A Flexible and Fast Software Supported Hardware Logging approach for NVM

Seunghee Shin (North Carolina State University); Satish Kumar Tirukkovalluri (North Carolina State University); James Tuck (North Carolina State University); Yan Solihin (North Carolina State University);

Speaker: Seunghee Shin, North Carolina State University

Extended abstract

Slides

Abstract Emerging non-volatile memory (NVM) technologies, such as phasechange memory, spin-transfer torque magnetic memory, memristor, and 3D Xpoint, are encouraging the development of new architectures that support the challenges of persistent programming. An important remaining challenge is dealing with the high logging overheads introduced by durable transactions. Here, we propose a new logging approach, Proteus, for durable transactions that achieves the favorable characteristics of both prior software and hardware approaches. Like software, it has no hardware constraint limiting the number of transactions or logs available to it, and like hardware, it has very low overhead. Our approach introduces two new instructions and hardware support, primarily within the core, to manage the execution of new instructions. We also propose a novel optimization at the memory controller that is enabled by a persistent write pending queue in the memory controller. We drop log updates that have not yet written back to NVMM by the time a transaction is considered durable. We compared our design against state-of-the-art hardware logging, ATOM, and a software only approach. Our experiments show that Proteus improves performance by 1.44-1.47× depending on configuration compared to a system without hardware logging and 9-11% faster than ATOM. A significant advantage of our approach is dropping writes to the log when they are not needed. On average, ATOM makes 3.4× more writes to memory than our design.

Speaker bio am currently a Ph.D. student in Electrical and Computer Engineering department at North Carolina State University under Dr. Yan Solihin’s advising. I am expecting to complete my Ph.D. study in summer, 2018. In ECE department, I belong to Computer Architecture and Systems group where my primary research interests lie in memory systems. I am graduating this year (2018) and currently looking for a full-time position.

Failure-atomic Synchronization-free Regions
Vaibhav Gogte (University of Michigan, Ann Arbor); Stephan Diestelhorst (ARM); William Wang (ARM); Satish Narayanasamy (University of Michigan, Ann Arbor); Peter M. Chen (University of Michigan, Ann Arbor); Thomas F. Wenisch (University of Michigan, Ann Arbor);

Extended abstract

Failure-atomic Synchronization-free Regions

Vaibhav Gogte (University of Michigan, Ann Arbor); Stephan Diestelhorst (ARM); William Wang (ARM); Satish Narayanasamy (University of Michigan, Ann Arbor); Peter M. Chen (University of Michigan, Ann Arbor); Thomas F. Wenisch (University of Michigan, Ann Arbor);

Speaker: Vaibhav Gogte, University of Michigan, Ann Arbor

Extended abstract

Abstract Nascent persistent memory (PM) technologies promise the performance of DRAM with the durability of disk, but how best to integrate them into programming systems remains an open question. Recent work extends language memory models with a persistency model prescribing semantics for updates to PM. These semantics enable programmers to design data structures in PM that are accessed like memory and yet are recoverable upon crash or failure. Alas, we find the semantics and performance of existing approaches unsatisfying. Existing approaches require high-overhead mechanisms, are restricted to certain synchronization constructs, provide incomplete semantics, and/or may recover to state that cannot arise in fault-free execution. We propose persistency semantics that guarantee failure atomicity of synchronization-free regions---program regions delimited by synchronization operations. Our approach provides clear semantics for the PM state recovery code may observe and extends C++11's "sequential consistency for data-race-free" guarantee to post-failure recovery code. We investigate two designs for failure-atomic SFRs that vary in performance and the degree to which commit of persistent state may lag execution. We demonstrate both approaches in LLVM v3.6.0 and compare to a state-of-the-art baseline to show performance improvement up to 87.5% (65.5% avg).

Speaker bio Vaibhav Gogte is a fourth-year PhD student in the Computer Science and Engineering department at University of Michigan and works with Prof. Thomas Wenisch. He is currently working on implementing the architecture and language support for integrating non-volatile memories into future computing systems. He received his bachelors degree from BITS, Pilani, India and has previously worked at Texas Instruments, Bangalore.

4:40 pm – 4:50 pm