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NVMW 2016

Program

The program below is preliminary and may change before the workshop.
A printable version of the program can be found here.

Sunday, March 6

1:00pm - 4:00pm
Tutorial
Price Center Ballroom East

Constrained Coding for Non-volatile Memories
Paul Siegel
CMRR
Slides

6:00pm - 9:00pm
Reception
Sheraton Hotel


Monday, March 7

7:45am - 8:45am
Continental Breakfast
Price Center Ballroom East

8:45am - 9:00am
Opening Remarks
Price Center Ballroom East


10:00am - 10:30am
Break

10:30am - 12:10pm
Session I: LDPC Codes
Price Center Ballroom East

Chair: Amit Berman

Designing and Encoding QC-LDPC Codes using Matrices over Commutative Rings
SanDisk
Ishai Ilani
Slides Abstract
High Speed Soft Decision Decoding Architecture for Triple Level Cell NAND Flash Memory
HGST, a Western Digital Company
Seung-Hwan Song, Kiran Gunnam, Minghai Qin, Luiz Franca-Neto, Robert Mateescu, Chenfeng Zhang, Rick Barndt, Zvonimir Bandic
Slides Abstract
Edge-Based Scheduling for Decoding Non-Binary LDPC Codes for MLC Flash Memories
Singapore University of Technology and Design∗, †
Cai Kui∗, Chaudhry Adnan Aslam†, Yong Liang Guan†
Slides
On the Application of Non-binary LDPC Codes to Flash Memories and Their Hardware Complexities
SanDisk
Xinmiao Zhang
Slides Abstract
Highly Reliable Techniques for TLC NAND Flash Memory
Chuo University, Department of Electrical, Electronic, and Communication Engineering, Japan
Atsuro Kobayashi, Tsukasa Tokutomi, Ken Takeuchi
Slides

12:10pm - 1:40pm
Lunch/Poster Session
Price Center Ballroom B

1:40pm - 3:00pm
Session II: NVM Efficiency and Performance
Price Center Ballroom East

Chair: Xinmiao Zhang

Energy Aware Persistence: Reducing the Energy Overheads of Persistent Memory
Georgia Institute of Technology
Sudarsun Kannan, Moin Qureshi, Ada Gavrilovska, Karsten Schwan
Slides
A Selective Overwrite Scheme to Mitigate Write Disturbance for Energy Efficient MLC STT-RAM
University of Central Florida∗, Florida International University†, University of Pittsburgh‡
Xunchao Chen∗, Navid Khoshavi∗, Ronald F. DeMara∗, Jun Wang∗, Wujie Wen†, Yiran Chen‡ Abstract
Modified-Move-To-Front: A Practical Data Compression Scheme for Non-Volatile Memories
University of Pittsburgh∗, Intel Corporation†
Poovaiah M. Palangappa∗, Ravi H. Motwani†, Kartik Mohanram∗
Slides
Evaluating performance of storage class memory through FPGA emulation
LLNL
Scott Lloyd, Maya Gokhale
Slides Abstract
Session III: Devices and Applications
Price Center Ballroom West

Chair: Arun Kanuparthi

Random Number Generation and Analog-to-Digital Conversion Based on a Magnetic Tunnel Junction
HGST Research∗, University of Minnesota†
Won Ho Choi∗, Yang Lv†, Jongyeon Kim†, Hoonki Kim†, Abhishek Deshpande†, Gyuseong Kang†, Jian-Ping Wang†, Chris H. Kim†
Slides Abstract
Triple Memory Cell with High Area Density and Energy Efficiency
UCSBBEI HANG University, CHINA
Linuo Xue, Yuanqing Cheng
Slides Abstract
ReRAM Crossbar based Cellular Neural Network for High Efficient Computing
Georgia Institute of Technology
Yun Long, Saibal Mukhopadhyay
Slides Abstract
Design of a NVRAM Specialized Degree Aware Dynamic Graph Data Structure
Tokyo Institute of Technology∗, Lawrence Livermore National Laboratory†
Keita Iwabuchi∗, Roger Pearce†, Brian Van Essen†, Maya Gokhale†, Satoshi Matsuoka∗
Slides

3:00pm - 3:20pm
Break

3:20pm - 5:00pm
Session IV: System Support NVMs
Price Center Ballroom East

Chair: Scott Lloyd

Supporting Superpages in Non-Contiguous Physical Memory
Intel∗, Univ. of Pittsburgh†
Yu Du∗, Miao Zhou†, Bruce R. Childers†, Daniel Mosse†, Rami Melhem†
MSUFS: Towards Joint Management of Memory and File on Storage Class Memory
San Diego State University
Deng Zhou, Wei Wang, Wen Pan, Tao Xie
Slides Abstract
Using Nonvolatile Pooled Memory Buffers In NVM Express over Fabrics Systems
PMC
Oren Berman, Stephen Bates
Slides Abstract
Tuning Memory-Mapped I/O with Non-Native Page Sizes for Data-Intensive Applications
Lawrence Livermore National Laboratory
Brian Van Essen, Ming Jiang, Maya Gokhale
Slides Abstract
Characterizing the Overhead of Software-Managed Hybrid Main Memory
University of Pittsburgh
Santiago Bock, Bruce Childers, Rami Melhem, Daniel Mosse
Slides Abstract
Session V: Lifetime Improving Codes
Price Center Ballroom West

Chair: Ishai Ilani

d-imbalance WOM Codes for Reduced Inter-Cell Interference in Multi-Level NVMs
Technion– Israel Institute of TechnologyTechnion – Israel Institute of Technology
Evyatar Hemo, Yuval Cassuto
Slides Abstract
The Devil is in the Details: Implementing Flash Page Reuse with WOM Codes
Johannes Gutenberg– Universität∗, Technion†, Caltech‡, Johannes Gutenberg – Universität◊
Fabio Margaglia∗, Gala Yadgar†, Eitan Yaakobi†, Yue Li‡, Assaf Schuster†, André Brinkmann◊
Slides Abstract
Codes Correcting Erasures and Deletions for Rank Modulation
UIUC∗, Technion†, Caltech‡, UCLA◊
Ryan Gabrys∗, Eitan Yaakobi†, Farzad Farnoud‡, Fred Sala◊, Jehoshua Bruck‡, Lara Dolecek◊
Slides Abstract
Error Characterization and Mitigation for 16nm MLC NAND Flash Memory under Total Ionizing Dose Effect
EE, Caltech∗, NASA JPL, Caltech†
Yue Li∗, Douglas J. Sheldon†, Andre S. Ramos∗, Jehoshua Bruck∗
Slides
Error-Correcting Codes for Radiation-Induced Error Patterns in Flash Memories
UCLA∗, JPL†
Frederic Sala∗, Clayton Schoeny∗, Dariush Divsalar†, Lara Dolecek∗
Slides Abstract

5:00pm - 6:30pm
Travel to Banquet

6:30pm - 9:00pm
Banquet
Mister A's, Downtown, San Diego


Tuesday, March 8

7:45am - 8:45am
Continental Breakfast
Price Center Ballroom East

8:45am - 9:00am
Opening Remarks
Price Center Ballroom East

9:00am - 10:00am
Keynote
Price Center Ballroom East

Wicked Fast Storage and Beyond
Frank Hady
Intel

10:00am - 10:30am
Break

10:30am - 12:10pm
Session VI: Managing and Accessing Non-Volatile Main Memory
Price Center Ballroom East

Chair: Hiroko Midorikawa

NOVA: A Log-structured File System for Hybrid Volatile/Non-volatile Main Memories
UC San Diego
Jian Xu, Steven Swanson
Slides Abstract
LUMFS: A Lightweight User-Mode File System for Storage Class Memory
Huawei Technologies
Yuangang Wang, Jun Xu, Licheng Chen, Yongbing Huang Abstract
Practical Persistence for Multi-threaded Applications
Purdue University and Hewlett Packard Labs∗, Hewlett Packard Labs†, Purdue University and TU Darmstadt‡
Terry Ching-Hsiang Hsu∗, Helge Brügner†, Indrajit Roy†, Kimberly Keeton†, Patrick Eugster‡
Slides Abstract
High-performance transactions for persistent memories
University of MIchigan∗, Snowflake Computing†, ARM‡, University of Michigan◊
Aasheesh Kolli∗, Steven Pelley†, Ali Saidi‡, Peter M. Chen◊, Thomas F. Wenisch◊
Exploiting Program Semantics to Place Data in Hybrid Memory
Institute of Computing Technology, Chinese Academy of Sciences∗, Chalmers University of Technology†
Wei Wei∗, Dejun Jiang∗, Sally A. McKee†, Jin Xiong∗, Mingyu Chen∗
Slides Abstract

12:10pm - 1:40pm
Lunch/Poster Session
Price Center Ballroom B

1:40pm - 3:00pm
Session VII: Coding Techniques
Price Center Ballroom East

Chair: Ravi Motwani

Shaping Codes for Structured Data
ECE, UCSD
Yi Liu, Paul H. Siegel
Slides Abstract
On the Channel Quantization for NAND Flash Memories
Korea Advanced Institute of Science and Technology (KAIST)
Daesung Kim, Suhwang Jeong, Jeongseok Ha
Slides Abstract
Coding for 3D Vertical Flash Memory
Carnegie Mellon University∗, HGST†
Yongjune Kim∗, Robert Mateescu†, Seung-Hwan Song†, Zvonimir Bandic†, B. V. K. Vijaya Kumar∗
Slides Abstract
Coding for DNA-Based Storage
UIUC∗, Nanyang Technological University†, Technion‡
Ryan Gabrys∗, Han Mao Kiah†, Olgica Milenkovic∗, Gregory Puleo∗, Eitan Yaakobi‡, Seyed M.T. Yazdi∗
Slides Abstract
Session VIII: Solid State Disks
Price Center Ballroom West

Chair: Arup De

Develop A Fast Flash Translation Layer by Exploiting Block-Level I/O Correlation

Jian Zhou, Jun Wang, Wu Fei, You Zhou, Changsheng Xie
Slides Abstract
Application-Driven Flash Translation Layers on Open-Channel SSDs
CNEX Labs
Javier Gonzalez, Matias Bjørling, Seongno Lee, Charlie Dong, Yiren Ronnie Huang
Slides Abstract
Index Integrated FTL for Multi-level Key-value Cache
samsung
Byoung Young Ahn, I. Stephen Choi, Yang-Suk Kee
Minimizing Flash I/O Traffic with Explicit I/Os for Efficient Out-of-Core Algorithms
Seikei University
Hiroko Midorikawa Abstract

3:00pm - 3:20pm
Break

3:20pm - 5:00pm
Session IX: Modeling
Price Center Ballroom East

Chair: Erich Haratsch

Channel Models for Multi-Level Cell Flash Memories Based on Empirical Error Analysis
University of California San Diego, La Jolla, CA, USA∗, Toshiba Corporation, Japan†
Veeresh Taranalli∗, Hironori Uchikawa†, Paul H. Siegel∗
Slides Abstract
Dynamic Voltage Allocation with Quantized Voltage Levels and Simplified Channel Modeling
University of California, Los Angeles
Haobo Wang, Nathan Wong, Richard D. Wesel
Slides Abstract
Flash Channel Modeling and Design Optimization: A Renewal-Theoretic Approach
University of Hawaii at Manoa∗, Seagate Technology†
Meysam Asadi∗, Erich F. Haratsch†, Aleksander Kavcic∗, Narayana P. Santhanam∗
Slides Abstract
Random Read Scheme for Minimal Maximum-Level Programming in Non-Volatile Memory
Samsung
Amit Berman
Slides
Models and Algorithms under Asymmetric Read and Write Costs
Carnegie Mellon Univeristy∗, Georgetown University†, University of California, Berkeley‡
Guy E. Blelloch∗, Jeremy T. Fineman†, Phillip B. Gibbons∗, Yan Gu∗, Julian Shun‡
Slides Abstract
Session X: Integrating NVMs into Systems
Price Center Ballroom West

Chair: Hung-Wei Tseng

Referencing Data Across a Distributed Non-Volatile Memory Fabric
Hewlett Packard Enterprise∗, Hewlett Packard Laboratories†, self employed‡
Mesut Kuscu∗, Jacqueline Bredenberg†, Tuan Tran†, Charles Johnson†, Harumi Kuno†, Bill Scherer∗, Joseph Tucek†, Wey Guy‡, Joao Ambrosi∗, Stan Park† Abstract
FlashNet: A Unified High-Performance IO Stack
IBM Research Zurich and ETH Zurich∗, IBM Research Zurich†, ETH Zurich‡
Animesh Trivedi∗, Nikolas Ioannou†, Bernard Metzler†, Patrick Stuedi†, Jonas Pfefferle∗, Ioannis Koltsidas†, Thomas R. Gross‡
Slides
Approaching 1 us I/O Access Latency with Orion
HGST, a Western Digital company
Arup De, Martin Lueker-Boden, Dejan Vucinic, Qingbo Wang, Zvonimir Bandic
Slides Abstract
A Processing-in-Memory Architecture for Bulk Bitwise Operations in Emerging Non-volatile Memories
UCSB∗, HP lab†, UCSC‡, Qualcomm◊
Shuangchen Li∗, Cong Xu†, Jishen Zhao‡, Yu Lu◊, Yuan Xie∗ Abstract
PRIME: Processing In ReRAM-based Main Memory
University of California Santa Barbara∗, Nvidia Corporation†, HP Labs‡, University of California Santa Cruz◊, Tsinghua University, Beijing
Ping Chi∗, Shuangchen Li∗, Tao Zhang†, Cong Xu‡, Jishen Zhao◊, Yu Wang, Yongpan Liu, Yuan Xie∗
Slides Abstract