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NVMW 2013


The program below is preliminary and may change before the workshop.

Sunday, March 3

1:00pm - 4:00pm
Price Center Ballroom East

Signal Processing and Coding for Non-Volatile Memories
Andrew Jiang∗, Eitan Yaakobi†
Texas A&M∗, Caltech†

6:00pm - 9:00pm
Sheraton Hotel

Monday, March 4

7:45am - 8:45am
Continental Breakfast
Price Center Ballroom East

8:45am - 9:00am
Opening Remarks
Price Center Ballroom East

9:00am - 10:00am
Price Center Ballroom East

Progress in Development and Commercialization of Magnetoresistive RAM

10:00am - 10:45am

10:45am - 12:05pm
Session I: Architecture I
Price Center Ballroom East

Chair: Douglas Santry, NetApp

Data Dependent Sparing to Manage Better-Than-Bad Blocks
University of Pittsburgh∗, University of Pittsburgh and Samsung Electronics Co.†
Rakan Maddah∗, Sangyeun Cho†
Slides Abstract
TBF: A Memory-Efficient Replacement Policy for Flash-based Caches
NEC Laboratories America
Cristian Ungureanu, Biplob Debnath, Stephen Rago
Slides Abstract
Write Amplification and WOM Codes in Flash Memories
Purdue University∗, Japan Advanced Institute of Science and Technology†
Luojie Xiang∗, Brian M. Kurkoski†
QuickSAN: A Storage Area Network for Fast, Distributed, Solid State Disks
Adrian Caulfield

12:05pm - 1:45pm
Lunch/Poster Session
Price Center Ballroom B

1:45pm - 3:05pm
Session II: Applications I
Price Center Ballroom East

Chair: Robert Sinkovits, SDSC

Querying Persistent Graphs using Solid State Storage
Ecole Polytechnique Federale de Lausanne∗, IBM T.J. Watson Research Center†
Manos Athanassoulis∗, Bishwaranjan Bhattacharjee†, Mustafa Canim† Abstract
RRAM Devices for Large Neuromorphic Systems
Dept of Electrical Engineering, IIT Bombay∗, IBM T J Watson Research Center†
Bipin Rajendran∗, Yong Liu†, Jae-sun Seo†, Kailash Gopalakrishnan†, Leland Chang†, Daniel Friedman†
HW/SW Architecture for Speech Recognition Acceleration
Spansion, Inc.
Richard Fastow, Stephan Rosner, Venkat Natarajan, Qamrul Hasan
Pomace: a Grappa for Non-Volatile Memory
University of Washington∗, University of Washington, Pacific Northwest National Laboratory†
Jacob Nelson∗, Brandon Holt∗, Brandon Myers∗, Preston Briggs∗, Luis Ceze∗, Simon Kahan†

3:05pm - 3:50pm

3:50pm - 5:30pm
Session IV: Architecture II
Price Center Ballroom East

Chair: Nisha Talagala, FusionIO

Constructing Large and Fast Multi-Level Cell STT-MRAM based Cache for Embedded Processors
University of Pittsburgh
Lei Jiang, Bo Zhao, Youtao Zhang
FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory
University of Pittsburgh
Lei Jiang, Youtao Zhang, Bruce R. Childers
Admission Polices for Solid State Cache Devices
Greg Gillis, Swaminathan Sundararaman, Nisha Talagala, Amar Mudrankit
Slides Abstract
Analysis of Flash Cleaning

Slides Abstract
Minerva: A Compute Capable SSD Architecture for Next-Generation Non-Volatile Memories
Arup De∗, Maya Gokhale†, Rajesh Gupta‡
Session V: ECC I
Price Center Ballroom A

Chair: Brian Kurkoski, JAIST

Dynamic Voltage Allocation Based on Mutual Information for NAND Flash Memory
UCLA∗, Rensselaer Polytechnic Institute†
Richard Wesel∗, Tong Zhang†, Adam Williamson∗, Tsung-Yi Chen∗
Cell to Cell Interference Mitigation Techniques for Flash Memory
Seoul National University
Myeongwoon Jeon
Exploiting Variation within MLC NAND to Improve Post ECC reliability
Complexity Science DTC, University of Warwick & Siglead Europe Ltd.∗, Siglead Europe Ltd.†
Oliver Hambrey∗, Thomas Parnell† Abstract
Inter-cell Interference Free Codes for Read/Write in Flash Memories
ucsd∗, caltech and ucsd†
Minghai Qin∗, Eitan Yaakobi†
Slides Abstract
Correcting Errors in MLCs with Bit-fixing Coding
Texas A&M University
Anxiao (Andrew) Jiang, Yue Li
Slides Abstract

5:30pm - 6:00pm

6:30pm - 9:00pm
The Marine Room - 2000 Spindrift Drive, La Jolla, CA 92037 (

Tuesday, March 5

7:45am - 9:20am
Price Center Ballroom East

9:20am - 10:40am
Session VI: Architecture III
Price Center Ballroom East

Chair: Zvonimir Bandic, HGST

Linux Block IO: Introducing Multi-Queue SSD Access on Multicore Systems
IT University of Copenhagen∗, Fusion-io†
Matias Bjørling∗, Jens Axboe†, David Nellans†
From Filesystem Designer to Persistent Data Structure Designer: Enabling Safe Memory Management for Byte-addressable NVRAM
Carnegie Mellon University∗, Intel Labs†, HP Labs‡, Maginatics◊
Iulian Moraru∗, David Andersen∗, Michael Kaminsky†, Parthasarathy Ranganathan‡, Niraj Tolia◊
bcache: Efficient Block Caching on SSDs
Google Inc
Kent Overstreet, Adam Berkan, Ricky Benitez Abstract
Utilizing Retired Pages for Improved Write Capacity of Solid State Drives
Amit Berman
Slides Abstract

10:50am - 12:10pm
Session VII: Devices II
Price Center Ballroom A

Chair: Ming Gu, iWatt

Access-Devices based on Mixed-Ionic-Electronic-Conduction (MIEC) Materials for Multi-Layer Crosspoint-Memory: Yield, Speed, and Scaling
IBM Almaden Research Center
Alvaro Padilla, Kumar Virwani, Rohit S. Shenoy, Geoffrey W. Burr, Bulent N. Kurdi
Dual-Port PCM Architecture for Network Processing
University of Pittsburgh
Jiayin Li, David Dgien, Nathan A Hunter, Yirong Zhao
Sneak-Path Constraints in Memristor Crossbar Arrays
Technion Israel Institute of Technology
Yuval Cassuto, Shahar Kvatinsky
High-performance STT-MRAM and Its Integration for Embedded Cache Memory
Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Kouji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi
Slides Abstract

12:10pm - 1:00pm
Lunch/Poster Session
Price Center Ballroom B

2:40pm - 3:00pm

3:00pm - 4:30pm
Stuart Collection Tour