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NVMW 2013

Program

The program below is preliminary and may change before the workshop.

Sunday, March 3

1:00pm - 4:00pm
Tutorial
Price Center Ballroom East

Signal Processing and Coding for Non-Volatile Memories
Andrew Jiang∗, Eitan Yaakobi†, Jason Bellorado‡
Texas A&M∗, Caltech†, Link-a-Media‡
Slides

6:00pm - 9:00pm
Reception
Sheraton Hotel


Monday, March 4

7:45am - 8:45am
Continental Breakfast
Price Center Ballroom East

8:45am - 9:00am
Opening Remarks
Price Center Ballroom East

9:00am - 10:00am
Keynote
Price Center Ballroom East

Progress in Development and Commercialization of Magnetoresistive RAM
Jon Slaughter
VP of Technology R&D, Everspin Technologies

10:00am - 10:45am
Break

10:45am - 12:05pm
Session I: Architecture I
Price Center Ballroom East

Chair: Douglas Santry, NetApp

Data Dependent Sparing to Manage Better-Than-Bad Blocks
University of Pittsburgh∗, University of Pittsburgh and Samsung Electronics Co.†
Rakan Maddah∗, Sangyeun Cho†, Rami Melhem∗
Slides Abstract
TBF: A Memory-Efficient Replacement Policy for Flash-based Caches
NEC Laboratories America
Cristian Ungureanu, Biplob Debnath, Stephen Rago, Akshat Aranya
Slides Abstract
Write Amplification and WOM Codes in Flash Memories
Purdue University∗, Japan Advanced Institute of Science and Technology†, Caltech‡
Luojie Xiang∗, Brian M. Kurkoski†, Eitan Yaakobi‡
Slides
QuickSAN: A Storage Area Network for Fast, Distributed, Solid State Disks
UCSD
Adrian Caulfield, Steven Swanson
Slides

12:05pm - 1:45pm
Lunch/Poster Session
Price Center Ballroom B

1:45pm - 3:05pm
Session II: Applications I
Price Center Ballroom East

Chair: Robert Sinkovits, SDSC

Querying Persistent Graphs using Solid State Storage
Ecole Polytechnique Federale de Lausanne∗, IBM T.J. Watson Research Center†, Columbia University‡
Manos Athanassoulis∗, Bishwaranjan Bhattacharjee†, Mustafa Canim†, Kenneth A. Ross‡ Abstract
RRAM Devices for Large Neuromorphic Systems
Dept of Electrical Engineering, IIT Bombay∗, IBM T J Watson Research Center†
Bipin Rajendran∗, Yong Liu†, Jae-sun Seo†, Kailash Gopalakrishnan†, Leland Chang†, Daniel Friedman†, Mark Ritter†
HW/SW Architecture for Speech Recognition Acceleration
Spansion, Inc.
Richard Fastow, Stephan Rosner, Venkat Natarajan, Qamrul Hasan, Jens Olson
Slides
Pomace: a Grappa for Non-Volatile Memory
University of Washington∗, University of Washington, Pacific Northwest National Laboratory†
Jacob Nelson∗, Brandon Holt∗, Brandon Myers∗, Preston Briggs∗, Luis Ceze∗, Simon Kahan†, Mark Oskin∗
Slides
Session III: Devices I
Price Center Ballroom A

Chair: Christophe Chevallier, Rambus

Architecting Low Power Crossbar-Based Memristive RAM
University of California, Santa Barbara
Miguel Angel Lastras-Montaño, Amirali Ghofrani, Kwang-Ting Cheng Abstract
An ultra-compact, floating-gate non-volatile current memory array with less than 150ppm/K temperature sensitivity and over 80dB programming range
iWatt Inc.Michigan State University
Ming Gu, Shantanu Chakrabartty
Slides Abstract
A 12 MHz, Sub Microamps Leakage and Low Active Power 64KB FRAM With Novel Design Techniques
Texas Instruments
Subir Chowdhury
Slides Abstract
A High Resolution Nonvolatile Analog Memory Ionic Devices
UCSB
Ligang Gao, Fabien Alibart, Dmitri B. Strukov Abstract

3:05pm - 3:50pm
Break

3:50pm - 5:30pm
Session IV: Architecture II
Price Center Ballroom East

Chair: Nisha Talagala, FusionIO

Constructing Large and Fast Multi-Level Cell STT-MRAM based Cache for Embedded Processors
University of Pittsburgh
Lei Jiang, Bo Zhao, Youtao Zhang, Jun Yang
Slides
FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory
University of Pittsburgh
Lei Jiang, Youtao Zhang, Bruce R. Childers, Jun Yang
Slides
Admission Polices for Solid State Cache Devices
Fusion-io
Greg Gillis, Swaminathan Sundararaman, Nisha Talagala, Amar Mudrankit, Jonathan Ludwig
Slides Abstract
Analysis of Flash Cleaning
Northeastern University
Peter Desnoyers
Slides Abstract
Minerva: A Compute Capable SSD Architecture for Next-Generation Non-Volatile Memories
UCSD/LLNL∗, LLNL†, UCSD‡
Arup De∗, Maya Gokhale†, Rajesh Gupta‡, Steven Swanson‡
Slides
Session V: ECC I
Price Center Ballroom A

Chair: Brian Kurkoski, JAIST

Dynamic Voltage Allocation Based on Mutual Information for NAND Flash Memory
UCLA∗, Rensselaer Polytechnic Institute†
Richard Wesel∗, Tong Zhang†, Adam Williamson∗, Tsung-Yi Chen∗, Kasra Vakalinia∗
Slides
Cell to Cell Interference Mitigation Techniques for Flash Memory
Seoul National University
Myeongwoon Jeon, Jungwoo Lee
Slides
Exploiting Variation within MLC NAND to Improve Post ECC reliability
Complexity Science DTC, University of Warwick & Siglead Europe Ltd.∗, Siglead Europe Ltd.†, Mathematics Institute, University of Warwick & Siglead Europe Ltd.‡
Oliver Hambrey∗, Thomas Parnell†, Oleg Zaboronski‡ Abstract
Inter-cell Interference Free Codes for Read/Write in Flash Memories
ucsd∗, caltech and ucsd†
Minghai Qin∗, Eitan Yaakobi†, Paul H. Siegel∗
Slides Abstract
Correcting Errors in MLCs with Bit-fixing Coding
Texas A&M UniversityCalifornia Institute of Technology
Anxiao (Andrew) Jiang, Yue Li, Jehoshua Bruck
Slides Abstract

5:30pm - 6:00pm
Break

6:30pm - 9:00pm
Banquet
The Marine Room - 2000 Spindrift Drive, La Jolla, CA 92037 (http://goo.gl/vbnPU)


Tuesday, March 5

7:45am - 9:20am
Breakfast
Price Center Ballroom East

9:20am - 10:40am
Session VI: Architecture III
Price Center Ballroom East

Chair: Zvonimir Bandic, HGST

Linux Block IO: Introducing Multi-Queue SSD Access on Multicore Systems
IT University of Copenhagen∗, Fusion-io†
Matias Bjørling∗, Jens Axboe†, David Nellans†, Philippe Bonnet∗
Slides
From Filesystem Designer to Persistent Data Structure Designer: Enabling Safe Memory Management for Byte-addressable NVRAM
Carnegie Mellon University∗, Intel Labs†, HP Labs‡, Maginatics◊, Nou Data Corporation
Iulian Moraru∗, David Andersen∗, Michael Kaminsky†, Parthasarathy Ranganathan‡, Niraj Tolia◊, Nathan Binkert
Slides
bcache: Efficient Block Caching on SSDs
Google Inc
Kent Overstreet, Adam Berkan, Ricky Benitez, Nauman Rafique Abstract
Utilizing Retired Pages for Improved Write Capacity of Solid State Drives
Technion
Amit Berman, Yitzhak Birk
Slides Abstract

10:50am - 12:10pm
Session VII: Devices II
Price Center Ballroom A

Chair: Ming Gu, iWatt

Access-Devices based on Mixed-Ionic-Electronic-Conduction (MIEC) Materials for Multi-Layer Crosspoint-Memory: Yield, Speed, and Scaling
IBM Almaden Research CenterIBM T. J. Watson Research Center
Alvaro Padilla, Kumar Virwani, Rohit S. Shenoy, Geoffrey W. Burr, Bulent N. Kurdi, Kailash Gopalakrishnan
Slides
Dual-Port PCM Architecture for Network Processing
University of Pittsburgh
Jiayin Li, David Dgien, Nathan A Hunter, Yirong Zhao, Kartik Mohanram
Sneak-Path Constraints in Memristor Crossbar Arrays
Technion Israel Institute of TechnologyCalifornia Institute of Technology
Yuval Cassuto, Shahar Kvatinsky, Eitan Yaakobi
Slides
High-performance STT-MRAM and Its Integration for Embedded Cache Memory
LEAP
Toshihiro Sugii, Yoshihisa Iba, Masaki Aoki, Hideyuki Noshiro, Kouji Tsunoda, Akiyoshi Hatada, Masaaki Nakabayashi, Yuuichi Yamazaki, Atsushi Takahashi, Chikako Yoshida
Slides Abstract

12:10pm - 1:00pm
Lunch/Poster Session
Price Center Ballroom B

1:00pm - 2:40pm
Session VIII: ECC II
Price Center Ballroom East

Chair: Eitan Yaakobi, Caltech

Digital Signal Processing for High Endurance Solid State Drives
Intel Corporation
Ravi Motwani, Chong Ong
Slides Abstract
Low-Energy and Low-Latency Error-Correction for Phase Change Memory
Case Western Reserve University
Xinmiao Zhang
Slides Abstract
Coding Scheme for Optimizing Random I/O Performance
Sandisk
Eran Sharon, Idan Alrod
Slides Abstract
Limited Magnitude Error Detecting Codes for Flash Memories
Hewlett Packard∗, Oregon State University†, King Saud University, Saudi Arabia‡
Noha Elarief∗, Bella Bose†, Samir Elmougy‡
Slides
Dynamic Threshold Schemes for Multi-Level Nonvolatile Memories
UCLA
Frederic Sala, Ryan Gabrys, Lara Dolecek
Slides Abstract

2:40pm - 3:00pm
Break

3:00pm - 4:30pm
Stuart Collection Tour