PROGRAM

Codes Correcting Under- and Over-Shift Errors in Racetrack Memories

Yeow MengChee (Nanyang Technological University);Han MaoKiah (Nanyang Technological University);AlexanderVardy (University of California San Diego);Van KhuVu (Nanyang Technological University);EitanYaakobi (Technion - Israel Institute of Technology);

Speaker:Van Khu Vu, Nanyang Technological University

AbstractRacetrack memory is a new technology which utilizes magnetic domains along a nanoscopic wire in order to obtain extremely high storage density. In racetrack memory, each magnetic domain can store a single bit of information, which can be sensed by a head. The memory has a tape-like structure which supports a shift operation that moves the domains to be read sequentially by the head. In order to increase the memory’s speed, prior work studied how to minimize the latency of the shift operation, while the no less important reliability of this operation has received only a little attention. There are two dominant kinds of errors in a shift operation, namely under-shift and limited-over-shift errors. In this work, we propose a coding scheme to combat these shift-errors. We first show that under-shift, limited-over-shift errors can be modeled as sticky-insertions, deletion-bursts of limited length, respectively. Therefore, in the model of multiple heads, a non-binary code correcting multiple bursts of deletions and any number of sticky-insertions can be used to tackle this problem. The goal of this work is to design such optimal codes.

Speaker bioHe received the B.Sc. degree in mathematics from Vietnam National University (VNU), Hanoi with the first rank in GPA of Class of 2010 and PhD degree in mathematics from School of Physical and Mathematical Sciences at Nanyang Technological University (NTU), Singapore in 2018. Between 2010-2012, he was a lecturer at Faculty of Mathematics, Mechanics and Informatics in VNU University of Sciences. Currently, he is a researcher in NTU, Singapore. His ultimate goal is to study and develop mathematical tools in combinatorics, algebra, knot theory, probability and statistic to invent original coding techniques and new algorithms to solve real world problems. In particular, his research currently concentrates on coding techniques for various data storage systems, such as Flash memories, Racetrack memories, Resistive memories and DNA based data storage.

Polar Coding for Selector-less Resistive Memories

MarwenZorgui (UC Irvine);MohammedFouda (UC Irvine);ZhiyingWang (UC Irvine);AhmedEltawil (UC Irvine);FadiKurdahi (UC Irvine);

Speaker:Zhiying Wang, University of California, Irvine

AbstractTransistor-based memories are rapidly approaching their maximum density per unit area. Resistive crossbar arrays enable denser memory due to the small size of switching devices. However, due to the resistive nature of these memories, they suffer from current sneak paths complicating the readout procedure. In this work, we propose an error-correcting scheme mitigating the sneak path effect based on polar codes. We describe the proposed code construction and show numerically the performance improvement in terms of bit error rate.

Speaker bioZhiying Wang received the B.Sc. degree in Information Electronics and Engineering from Tsinghua University in 2007, M. Sc. and Ph.D degrees in Electrical Engineering from California Institute of Technology in 2009 and 2013, respectively. She was a postdoctoral fellow in Department of Electrical Engineering, Stanford University. She is currently Assistant Professor at Center for Pervasive Communications and Computing, University of California, Irvine. Dr. Wang is the recipient of NSF Center for Science of Information (CSoI) Postdoctoral Research Fellow, 2013. She received IEEE Communication Society Data Storage Best Paper Award. Her research focuses on information theory, coding theory, with an emphasis on coding for data storage.

Resistive Memory Fully Compatible with Advanced CMOS Nodes

JeremyGuy (Crossbar Inc.);AmitPrakash (Crossbar Inc.);Sung HyunJo (Crossbar Inc.);

Speaker:Jérémy Guy, Crossbar Inc.

AbstractWe report the feasibility of high density Aluminum based Resistive memory (ReRAM) and its extremely good performances and behavior when coupled with optimized material stack. Sub 50nm devices integrated in 1T1R 2Mb array are offering exceptional advantages, including a Forming free switching, 400°C baking stability, outstanding 225°C retention and beyond 100k cycle endurance.

Speaker bioJérémy Guy was born in Paris in 1989, he received the Engineering degree in material science from the Institut National des Sciences Appliquées de Lyon (INSA), as well as M.S. degree in microelectronic and embedded system from INSA, and the University of Lyon, Lyon, in 2012. He completed his Ph.D degree in physics and nano-electronics, with both the Institut National Polytechnique de Grenoble, and CEA – Leti, Grenoble, France in 2015. He joined Crossbar, Santa Clara, CA, in 2016 in order to continue his career in nonvolatile memory technologies. He’s the author and co-author of multiple publications, journal articles and internationals patents relative to RRAM.

Current-Sensing Efficient Adder for Processing-in-Memory Design

JoonseopSim (University of California, San Diego);MohsenImani (University of California, San Diego);

Speaker:Mohsen Imani, University of California, Sandiego

AbstractInternet of Things (IoT) involves processing massive data. This poses a huge challenge in the current computingsystems due to the limited memory bandwidth. Processingin-memory (PIM) is a promising candidate to minimize thisbottleneck and reduce the performance gap between proces-sor and memory latency. We proposeLUPIS(Latch-Up basedProcessing In-memory System) for nonvolatile memory (NVM). Unlike existing PIM techniques, which mainly focus on bitwiseoperation based computations and involve considerable latencyand area penalty, our design facilitates computations like addi-tion and multiplication with very low latency. This makes thesystem faster and more efficient as compared to the state-of-the-art technologies. We evaluate LUPIS at both circuit-leveland application-level. Our evaluations show that LUPIS can enhance the performance and energy efficiency by 62× and 484× respectively as compared to a recent GPGPU architecture. Compared to the state-of-the-art PIM accelerator, our design presents 12.7X and 20.9X improvement in latency and energy consumption with insignificant overhead of 21% for area increase and one cycle for latency delay.

Speaker bioMohsen Imani received his M.S. and BCs degrees from the School of Electrical and Computer Engineering at the University of Tehran in March 2014 and September 2011 respectively. From September 2014, he is a Ph.D. student in the Department of Computer Science and Engineering at the University of California San Diego, CA, USA. He is a project leader at System Energy Efficient Laboratory (SeeLab) where he is mentoring several graduate and undergraduate students on different computer engineering projects from circuit to system level. Mr. Imani research focuses on computer architecture, machine learning, and brain-inspired computing.

To Cache Or To Bypass? A Fine Balance in The Emerging Memory Technology Era

KunalKorgaonkar (UC San Diego);IshwarBhati (Intel);HuichuLiu (Intel);JayeshGaur (Intel);SasikanthManipatruni (Intel);SreenivasSubramoney (Intel);TanayKarnik (Intel);StevenSwanson (UC San Diego);IanYoung (Intel);HongWang (Intel);

Speaker:Kunal Korgaonkar, UC San Diego

AbstractWith the availability of new memory technologies like MRAM and ReRAM, the days of SRAM only on-chip caches are likely coming to an end. In our recent work presented at ISCA 2018~\cite{Korgaonkar2018}, we showed the benefits of replacing the SRAMs of Last Level Caches (LLCs) with STT-MRAM in high-performance processors. Our work unearthed key findings regarding optimal caching/bypassing policies which are unlike those used in current state-of-the-art caching hierarchies. Relative to SRAM, the newer memory technologies can provide 2x to 4x capacity. However, utilizing this capacity to the fullest requires maintaining a fine balance between caching and bypassing. We found that in a hierarchy using emerging technology both caching and bypassing policies become levers to controlling the effective bandwidth (both read and write bandwidth) and the effective latency (affecting the hit rate and hence latency). As new memory technologies are being introduced, we believe maintaining a balance between caching and bypassing is likely to become even more relevant, not just for on-chip caches, but across the entire memory hierarchy.

Speaker bioKunal Korgaonkar is a PhD candidate at the CSE department at UC San Diego. As part of this thesis, he is designing scalable micro-architectures for systems using emerging memory technologies. He is advised by Prof. Steven Swanson. Kunal has a masters from IIT Madras, India (Contact email id - kkorgaon@ucsd.edu)

Challenges in Building and Deploying Disaggregated Persistent Memory

YizhouShan (Purdue University);YutongHuang (Purdue University);YiyingZhang (Purdue University);

Speaker:Yiying Zhang, Purdue University

AbstractByte-addressable non-volatile memory (NVM) such as 3D-Xpoint and the memristor provides persistence, close-to-DRAM performance, and high density. Apart from packaging NVMs in SSDs and using them as storage devices, NVMs can be used as memory. These usage models are often called non-volatile main memory or persistent memory (PM). We believe that a more cost-efficient and flexible way to deploy PM is to build PMs as stand-alone devices and to attach them directly to the datacenter network, a model we call disaggregated persistent memory, or DPM. Each DPM device has a network interface, a PM controller, and bulk PM. DPM shares many benefits with a more general disaggregated datacenter architecture. This work addresses the hardware and networking challenges in building and deploying DPMs.

Speaker bioYiying Zhang is an assistant professor in the School of Electrical and Computer Engineering at Purdue University. Her research interests span operating systems, distributed systems, datacenter networking, and computer architecture, with a focus on building software, hardware, and networking systems for next-generation datacenters. Her recent research interest is in datacenter resource disaggregation. Yiying received her Ph.D. from the Department of Computer Sciences at the University of Wisconsin-Madison under the supervision of Andrea and Remzi Arpaci-Dusseau and worked as a postdoctoral scholar at the University of California, San Diego before joining Purdue.

Hardware support for ACID Transactions in Persistent Memory

ArpitJoshi (Intel);VijayNagarajan (University of Edinburgh);MarceloCintra (Intel);StratisViglas (Google);

Speaker:Arpit Joshi, Intel

AbstractThe emergence of byte-addressable persistent (non-volatile) memory provides a low latency and high bandwidth path to durability. However, programmers need guarantees on what will remain in persistent memory in the event of a system crash. A widely accepted model for crash consistent programming is ACID transactions, in which updates within a transaction are made visible as well as durable in an atomic manner. However, existing software based proposals suffer from significant performance overheads. In this proposal, we support both atomic visibility and durability in hardware. We propose DHTM (durable hardware transactional memory) that leverages a commercial HTM to provide atomic visibility and extends it with hardware support for redo logging to provide atomic durability. Furthermore, we leverage the same logging infrastructure to extend the supported transaction size (from being L1-limited to LLC-limited) with only minor changes to the coherence protocol. Our evaluation shows that DHTM outperforms the state-of-the-art by an average of $21\%$ to $25\%$ on TATP, TPC-C and a set of microbenchmarks. We believe DHTM is the first complete and practical hardware based solution for ACID transactions that has the potential to significantly ease the burden of crash consistent programming.

Programming Storage Controllers with OX

Ivan LuizPicoli (IT University of Copenhagen);PinarTözün (IT University of Copenhagen);AndrzejWasowski (IT University of Copenhagen);PhilippeBonnet (IT University of Copenhagen);

Speaker:Ivan Luiz Picoli, IT University of Copenhagen

AbstractOffloading processing to storage is a means to minimize data movement and efficiently scale up processing capabilities for increasing data volumes. Existing approaches, e.g., from ScaleFlux or NGX, push functions to a SSD on top of a generic FTL. In previous work, we have argued that generic FTLs are not desirable because of inefficient redundancies and missed opportunities for optimization across layers. In this paper, we argue that offloading processing to storage is a great opportunity for cross layer optimization, if we have an appropriate framework for programming the storage controller. We discuss the lessons we learnt programming the storage controller with the OX template.

Speaker bioIvan Luiz Picoli is finishing his PhD at the IT University of Copenhagen. Ivan worked at Tsinghua University and Microsoft Research. He contributed to the DFC open source initiative. His PhD scholarship is funded by Brazilian CAPES.

Designing a User-Friendly Java NVM Framework

ThomasShull (University of Illinois at Urbana-Champaign);JianHuang (University of Illinois at Urbana-Champaign);JosepTorrellas (University of Illinois at Urbana-Champaign);

Speaker:Thomas Shull, University of Illinois at Urbana-Champaign

AbstractByte addressable, non-volatile memory (NVM) is emerging as a revolutionary technology that provides near-DRAM performance and scalable memory capacity. To facilitate its usability, many NVM programming models have been proposed. However, most of them require programmers to explicitly specify the data structures or objects that should reside in NVM. Such a limitation inevitably increases the burden on programmers, complicates development, and further introduces correctness and performance bugs. To rectify this situation, we propose a new user-friendly Java NVM framework. Because our model is defined at a high level, it is intuitive, not prone to user bugs, and is flexible enough to allow language implementers to perform many optimizations while still adhering to its requirements. We implement a persistent version of memcached in our framework and find that its performance exceeds existing Java offerings and requires minimal program modifications.

Speaker bioThomas Shull is a PhD student at the University of Illinois at Urbana-Champaign, working under the guidance of Josep Torrellas. His research interests include the implementation of managed languages, architecture, and emerging memory technologies. Currently, he is working to develop a new NVM programming model and implementation for managed languages which achieves the trinity of programmability, safety, and performance.

Redesigning LSMs for Nonvolatile Memory with NoveLSM

SudarsunKannan (Rutgers University);NitishBhat (Georgia Tech);AdaGavrilovska (Georgia Tech);AndreaArpaci-Dusseau (University of Wisconsin Madison);RemziArpaci-Dusseau (University of Wisconsin Madison);

Speaker:Sudarsun Kannan, Rutgers University

AbstractWe present NoveLSM, a persistent LSM-based key-value storage system designed to exploit non-volatile memories and deliver low latency and high throughput to applications. We utilize three key techniques – a byte-addressable skip list, direct mutability of persistent state, and opportunistic read parallelism – to deliver high performance across a range of workload scenarios. Our analysis with popular benchmarks and real-world workload reveal up to a 3.8x and 2x reduction in write and read access latency compared to LevelDB. Storing all the data in a persistent skip list and avoiding block I/O provides more than 5x and 1.9x higher write throughput over LevelDB and RocksDB. Recovery time improves substantially with NoveLSM’s persistent skip list.

Speaker bioSudarsun Kannan is an Assistant Professor at Rutgers University's Computer Science Department with a research focus on Operating Systems. More specifically, he works on problems relating to heterogeneous resource (memory, storage, and compute) management challenges and understanding their impact on large-scale applications. Before joining Rutgers, Sudarsun was a postdoc at the University of Wisconsin-Madison's Computer Science Department and graduated from the College of Computing, Georgia Tech. His thesis explored methods to support hardware heterogeneity in Operating Systems.

FAST and FAIR B+-Tree for Byte-Addressable Persistent Memory

Wook-HeeKim (UNIST);DeukyeonHwang (UNIST);JonghyeonYoo (Sungkyunkwan University);YoujipWon (KAIST);BeomseokNam (Sungkyunkwan University);

Speaker:Wook-Hee Kim, UNIST (Ulsan National Institute of Science and Technology)

AbstractThis extended abstract presents our FAST and FAIR B+-tree that redesigns insertion, deletion, rebalancing, and search algorithms such that tree structures can be modified in a failure-atomic fashion via a series of store and clflush instructions. We also present the performance of legacy binary T-tree that we modified for byte-addressable persistent memory. Our experimental results show the performance of T-tree is comparable to other state-of-the-art persistent indexes although its implementation is much simpler.

Speaker bioWook-Hee Kim is a postdoctoral researcher in the College of Software at Sungkyunkwan University. He received his Ph.D. and B.S. degree from Ulsan National Institute of Science and Technology (UNIST) in 2019 and 2013 respectively. His research interests include system software for non-volatile memories.