NVMW 2017

Program

The program below is preliminary and may change before the workshop.


Sunday, March 12

1:00pm - 4:00pm
Tutorial
Price Center East Ballroom

6:00pm - 9:00pm
Reception
Sheraton Hotel


Monday, March 13

7:45am - 8:45am
Continental Breakfast
Price Center East Ballroom

8:45am - 9:00am
Opening Remarks
Price Center East Ballroom


Paul H Siegel
UCSD

9:00am - 10:00am
Keynote
Price Center East Ballroom


Prof. H.-S. Philip Wong
Department of Electrical Engineering, Stanford University

10:00am - 10:30am
Break

10:30am - 12:30pm
Session I: Industry Perspectives
Price Center East Ballroom

Chair: Idan Alrod

The Evolution of NVM Express to Meet Cloud Determinism Requirements For NVM Devices
Intel Facebook
Amber Huffman, Chris Peterson
Virtual Reality as a Workload Requiring Very High Performance Non-Volatile Memory
Intel
Jianfang Zhu, Rick Coulson, Stephanie Jones, Frank Hady, Dale Juenemann
Using Crail for Analytics on disaggregated storage
IBM Research - Zurich
Patrick Stuedi, Jonas Pfefferle, Animesh Kumar Trivedi, Nikolas Ioannou, Radu Stoica, Bernard Metzler, Ioannis Koltsidas
Multi-Tenant I/O Isolation with Open-Channel SSDs
CNEX Labs
Javier González, Matias Bjørling
Andromeda: Building the Next-Generation High-Density Storage Interface for Successful Adoption
Microsoft∗, Microsoft Research†
Laura Caulfield∗, Michael Xing∗, Anirudh Badam†, Robin Alexander∗

12:30pm - 2:00pm
Lunch/Poster Session
Price Center Ballroom B

2:00pm - 3:20pm
Session II: Operating Systems and Runtimes for NVM
Price Center West Ballroom

Chair: Ameen Akel

Phoenix: Memory Speed HPC I/O with NVM
Georgia Tech
Pradeep Fernando, Sudarsun Kannan, Ada Gavrilovska, Karsten Schwan
CloudCache: On-demand Flash Cache Management for Cloud Computing
Parallel Machines∗, Arizona State University†, Google‡
Dulcardo Arteaga∗, Jorge Cabrera†, Jing Xu‡, Swaminathan Sundararaman∗, Ming Zhao†
NRCIO: NVM-aware RDMA-based Communication and I/O Schemes for Big Data Analytics
The Ohio State University
Xiaoyi Lu, Nusrat Islam, Md. Wasi-ur-Rahman, Dhabaleswar K. (DK) Panda
Twizzer: The Design and Implementation of a NVM Aware OS
UCSC
Matt Bryson, Daniel Bittman, Darrell Long, Ethan Miller
Session III: ECC Applications and ReRAM
Price Center East Ballroom

Chair: Erich Haratsch

A Flexible and Low-Complexity Local Erasure Recovery Scheme
Western Digital
Xinmiao Zhang
Leveraging Negative Differential Resistance for Low Power, High Reliability Resistive Memories
UCLA
Shaodi Wang, Andrew Pan, Cecile Grezes, Pedram Khalili Amiri, Kang L. Wang, Chi On Chui, Puneet Gupta
ReRAM-based SSD Performance Considering Verify-program Cycles and ECC Capabilities
Chuo University, Tokyo, Japan
Hirofumi Takishita, Yutaka Adachi, Ken Takeuchi
Physically Unclonable Function on NAND Flash Memory
Korea Advanced Institute of Science and Technology
Sangha Lee, Sangseok Yoon, Jeongseok Ha

3:20pm - 3:40pm
Break

3:40pm - 5:20pm
Session IV: Error Modeling and Error Mitigation Codes
Price Center West Ballroom

Chair: Andrew Jiang

On the Distribution of Bit Errors in NAND Flash Memories
CNEX Labs
Xiaojie Zhang, Patrick Lee, Ronnie Huang, Alan Armstrong
Dynamic Memory Error Model Estimation for Read and ECC Adaptations
Sandisk/Western Digital
Eran Sharon, Alex Bazarsky
Mutually Uncorrelated Codes for DNA Storage
Technion
Maya Levy, Eitan Yaakobi
Novel ICI-mitigation Codes for MLC NAND Flash Memory
UCSD
Osamu Torii, Paul Siegel
Detectors and Codes for Sneak-Path Interference in Resistive Arrays
Technion - Israel Institute of Technology
Yuval Ben-Hur, Yuval Cassuto
Session V: SSD Architecture and Management Policies
Price Center East Ballroom

Chair: Laura Caulfield

Static Garbage Collection Algorithms for Meta Data Updates in NAND Flash
WDC
Minghai Qin, Robert Mateescu, Qingbo Wang, Jing Booth, Stanley Chu, Cyril Guyot, Dejan Vucinic, Zvonimir Bandic
Thermostat: Keeping your DRAM hot and NVRAM cool
University of Michigan
Neha Agarwal, Thomas F. Wenisch
IOPS and QoS Analysis of DRAM/Flash-based and All-MRAM based NVRAM cards
University of Ferrara∗, Everspin Technologies†, Microsemi Corporation‡
Lorenzo Zuolo∗, Cristian Zambelli∗, Terry Hulett†, Ben Cooke†, Rino Micheloni‡, Piero Olivo∗
CacheDedup: In-line Deduplication for Flash Caching
Arizona State University∗, Florida International University†, Rensselaer Polytechnic Institute‡
Wenji Li∗, Gregory Jean-Baptiste†, Juan Riveros†, Giri Narasimhan†, Tong Zhang‡, Ming Zhao∗
WORT: Write Optimal Radix Tree for Persistent Memory Storage Systems
UNIST∗, Hongik University†
Se Kwon Lee∗, K. Hyun Lim†, Hyunsub Song∗, Beomseok Nam∗, Sam H. Noh∗

5:20pm - 6:30pm
Travel to Banquet

6:30pm - 9:00pm
Banquet
Coasterra


Tuesday, March 14

7:45am - 8:45am
Continental Breakfast
Price Center East Ballroom

8:45am - 9:00am
Opening Remarks
Price Center East Ballroom


Eitan Yaakobi
Technion

9:00am - 10:00am
Keynote
Price Center East Ballroom


Martin Fink
Chief Technical Officer, Western Digital Corporation

10:00am - 10:30am
Break

10:30am - 12:10pm
Session VI: LDPC Codes
Price Center East Ballroom

Chair: Yuval Cassuto

Non-Binary LDPC Code Optimization for Modern Storage Systems
UCLA
Ahmed Hareedy, Chinmayi Lanka, Lara Dolecek
Decoding Mapping Functions for High-Rate LDPC Codes
JAIST
Francisco Javier Cuadros Romero, Brian M. Kurkoski
Heterogeneous-Integrated LDPC ECC of TLC NAND Flash Memory for Read-Hot&Cold Mixed Data Storage
Chuo University
Toshiki Nakamura, Yoshiaki Deguchi, Atsuro Kobayashi, Ken Takeuchi
Modeling the effects of radiation induced soft errors on LDPC decoding
Department of Electrical Engineering, University of California, Los Angeles∗, Jet Propulsion Laboratory, California Institute of Technology†
Frederic Sala∗, Clayton Schoeny∗, Shahroze Kabir∗, Dariush Divsalar†, Lara Dolecek∗
An Upper Bounding Technique on the Error Floor Performance of LDPC Codes
Intel Corporation
Santhosh Kumar, Ravi H Motwani

12:10pm - 1:40pm
Lunch/Poster Session
Price Center Ballroom B

1:40pm - 3:00pm
Session VII: Database and File Systems
Price Center West Ballroom

Chair: Hung-Wei Tseng

HiKV: A Hybrid Index Key-Value Store for DRAM-NVM Memory Systems
Institute of Computing Technology, Chinese Academy of Science
Fei Xia, Dejun Jiang, Jin Xiong, Ninghui Sun
Towards a Single-Level Database Architecture on Non-Volatile Memory
TU Dresden&SAP SETU Dresden
Ismail Oukid, Wolfgang Lehner
Transforming Legacy File Systems into Persistent Memory Exploiting File Systems with MeLo@V
UNIST
Hyunsub Song, Young Je Moon, Se Kwon Lee, Sam H. Noh
Persistent Memory File System Characterization: A Hardware Perspective
UCSC∗, Western Digital†
Xiao Liu∗, Bhaskar Jupudi∗, Pankaj Mehra†, Jishen Zhao∗
Session VIII: Coding for Structured Data
Price Center East Ballroom

Chair: Brian Kurkoski

Performance of Shaping Codes for Flash Memory
Electrical and Computer Engineering Dept., University of California, San Diego
Yi Liu, Pengfei Huang, Paul H. Siegel
Error Correction by Natural Redundancy for Long Term Storage
Texas A&M University∗, Seagate Technology†, Caltech‡
Anxiao (Andrew) Jiang∗, Pulakesh Upadhyaya∗, Erich F. Haratsch†, Jehoshua Bruck‡
LDPC Decoding with Natural Redundancy
Texas A&M University
Pulakesh Upadhyaya, Anxiao (Andrew) Jiang
Modeling and Analysis of Joint Decoding of Language-Based Sources with Polar Codes
Texas A&M University
Ying Wang, Anxiao (Andrew) Jiang, Krishna R. Narayanan

3:00pm - 3:20pm
Break

3:20pm - 5:00pm
Session IX: Data Persistency
Price Center West Ballroom

Chair: Jishen Zhao

TARP: Translating Acquire-Release Persistency
University of Michigan∗, ARM†
Aasheesh Kolli∗, Vaibhav Gogte∗, Ali Saidi†, Stephan Diestelhorst†, Peter M. Chen∗, Satish Narayanasamy∗, Thomas F. Wenisch∗
Hands-Off Persistence System (HOPS)
University of Wisconsin-Madison∗, Hewlett Packard Enterprise†
Swapnil Haria∗, Sanketh Nalli∗, Michael M. Swift∗, Mark D. Hill∗, Haris Volos†, Kimberly Keeton†
WHISPER : Wisconsin-HPL Suite for Persistence
UW Madison∗, HP Labs†
Sanketh Nalli∗, Michael Swift∗, Swapnil Haria∗, Mark Hill∗, Haris Volos†, Kimberly Keeton†
Persistent Regions that Survive NVM Media Failure
Department of Computer Science, North Carolina State University∗, Technical University, Munich†, UC Santa Cruz‡, HPE Nonstop Research◊, Amazon, Palo Alto, CA, Hewlett Packard Labs
Onkar Patil∗, Mesut Kuscu†, Tuan Tran‡, Charles Johnson◊, Joseph Tucek, Harumi Kuno
Relaxing Persistent Memory Constraints with Hardware-Driven Undo+Redo Logging
UC Santa Cruz
Matheus Ogleari, Jishen Zhao, Ethan Miller
Session X: New NVM Architectures and Applications
Price Center East Ballroom

Chair: Rick Coulson

Non-volatile Content Addressable Memory for Computing Acceleration
University of California San Diego∗, University of California Berekely†
Mohsen Imani∗, Daniel Peroni∗, Abbas Rahimi†, Tajana Rosing∗
In-Memory Processing to Support Search-Based and Bitwise Computation
University of California San Diego
Mohsen Imani, Yeseong Kim, Tajana Rosing
Deep Network Acceleration with Memristor Crossbars
University of Utah∗, Hewlett Packard Labs†
Ali Shafiee∗, Anirban Nag∗, Naveen Muralimanohar†, Rajeev Balasubramonian∗, John Paul Strachan†, Miao Hu†, R. Stanley Williams†, Vivek Srikumar∗
Performance evaluation of scale-free graph algorithms
San Diego Supercomputer Center∗, Tokyo Institute of Technology†, Lawrence Livermore National Laboratory‡
Manu Shantharam∗, Keita Iwabuchi†, Pietro Cicotti∗, Laura Carrington∗, Maya Gokhale‡, Roger Pearce‡
SECRET: Smartly EnCRypted Energy EfficienT Non-Volatile Memories
University of Pittsburgh
Shivam Swami, Joydeep Rakshit, Kartik Mohanram