You are viewing an archived workshop website. The website for the latest workshop, NVMW 2017, can be found here

NVMW 2015

Program

The program below is preliminary and may change before the workshop.
A printable version of the program can be found here.

Sunday, March 1

1:00pm - 4:00pm
Tutorial
Price Center Ballroom East

The RAMCloud Storage System
John Ousterhout
Stanford University
Slides

6:00pm - 9:00pm
Reception
Sheraton Hotel


Monday, March 2

7:45am - 8:45am
Continental Breakfast
Price Center Ballroom East

8:45am - 9:00am
Opening Remarks
Price Center Ballroom East

9:00am - 10:00am
Keynote
Price Center Ballroom East

How NAND-based Technology is Transforming the Data Center
Bob Brennan
Samsung Senior Vice President and head of Samsung's Memory Solution Lab

10:00am - 10:30am
Break

10:30am - 11:50am
Session I: Rewriting Codes and Replication Codes
Price Center Ballroom East

Chair: Yuval Cassuto

Coding for Secure Write-efficient Memories

Qing Li, Anxiao (Andrew) Jiang
Slides Abstract
Write Once, Get 50% Free: Saving SSD Erase Costs Using WOM Codes
Technion
Gala Yadgar, Eitan Yaakobi, Assaf Schuster
Slides Abstract
Enhancing the Average Lifetime of Flash Memory by Lattice-Based WOM Codes
CMRR, University of California San Diego∗, HGST†
Bing Fan∗, Minghai Qin†, Paul Siegel∗
Slides
Joint Decoding of content-replication codes for flash memories
Dept. of Computer Sci.&Eng. Texas A&M UniversitySeagate Technology
Qing Li, Anxiao (Andrew) Jiang, Erich F. Haratsch
Slides Abstract
Session II: Solid State Disks
Price Center Ballroom West

Chair: Hung-Wei Tseng

Block-Level I/O Characteristics of Smartphone Applications and Their Implications for eMMC Design
San Diego State University
Deng Zhou, Tao Xie, Wei Wang
Slides Abstract
Linux Kernel Abstractions for Open-Channel Solid State Drives
IT University of Copenhagen
Matias Bjørling, Jesper Madsen, Javier Gonzalez, Philippe Bonnet
Slides Abstract
AppNVM: Software-Defined, Application-Driven SSD
IT University of Copenhagen∗, UCSD†
Matias Bjørling∗, Michael Wei†, Jesper Madsen∗, Javier Gonzalez∗, Steven Swanson†, Philippe Bonnet∗ Abstract
Using Flash SSDs as Main Memory Extension with a Locality-aware Algorithm
Seikei University
Hiroko Midorikawa Abstract

11:50am - 1:10pm
Lunch/Poster Session
Price Center Ballroom B

1:10pm - 2:10pm
Keynote
Price Center Ballroom East

Storage - Moving Towards Tailored Solutions
Phil Brace
Executive Vice President, Electronic Solutions at Seagate Technology
Slides

2:10pm - 2:20pm
Break

2:20pm - 3:40pm
Session III: Memory Hiearchies
Price Center Ballroom East

Chair: Brian Van Essen

Rethinking the Memory Hierarchy Design with Nonvolatile Memories
HP LabsUCSB
Jishen Zhao, Yuan Xie
Slides Abstract
A Case for STT-RAM Based Hybrid Buffer Design for Network-on-Chip
University of California, Santa Barbara
Jia Zhan, Yuan Xie
Slides Abstract
Designing a Fast and Reliable Main Memory with Memristor Technology
University of Utah∗, HP Labs†, University of Utah/ HP Labs‡
Manjunath Shevgoor∗, Naveen Muralimanohar†, Rajeev Balasubramonian‡
Slides
Energy-Efficient Inclusion Properties for STT-RAM Last-Level Caches
Pennsylvania State University∗, University of California at Santa Barbara†
Hsiang-Yun Cheng∗, Matt Poremba∗, Ivan Stalev∗, Yuan Xie†, Jack Sampson∗, Mary Jane Irwin∗
Session IV: Devices
Price Center Ballroom West

Chair: Shruti Patil

Modelling of the Threshold Voltage Distributions of Sub-20nm NAND Flash Memory
IBM Research - Zurich
Thomas Parnell, Nikolaos Papandreou, Thomas Mittelholzer, Haralampos Pozidis
Slides
Crossbar Resistive RAM for High Density Memory Applications
Crossbar Inc.
Sung Hyun Jo, Tanmay Kumar, Hagop Nazarian
Slides Abstract
Design a High-Performance Main Memory by Overcoming the Challenges of Crossbar Resistive Memory Architectures
Pennsylvania State University∗, HP Labs†, University of Utah‡, Arizona State University◊, University of California at Santa Barbara
Cong Xu∗, Dimin Niu∗, Naveen Muralimanohar†, Rajeev Balasubramonian‡, Tao Zhang∗, Shimeng Yu◊, Yuan Xie
HReRAM: A Hybrid Reconfigurable Resistive Random-Access Memory
University of California, Santa Barbara
Miguel Angel Lastras-Montano, Amirali Ghofrani, Kwang-Ting Cheng

3:40pm - 3:55pm
Break

3:55pm - 5:15pm
Session V: Data Compression and Shaping Codes
Price Center Ballroom East

Chair: Idan Alrod

Compression-Expansion Coding for MLC/TLC Non-volatile Memories
University of Pittsburgh
Poovaiah M. Palangappa, Kartik Mohanram
Incremental Error Recovery for Endurance and Energy Improvements in Non-Volatile Memories
University of Pittsburgh
Shivam Swami, Kartik Mohanram
Slides
Data Shaping for Improving Endurance and Reliability in Sub-20nm NAND
Sandisk
Eran Sharon, Stella Achtenberg, Idan Alrod, Avi Klein, Alon Eyal
Slides Abstract
Enhanced Error Correction via Language Processing
Texas A&M University∗, Caltech†
Anxiao (Andrew) Jiang∗, Yue Li†, Jehoshua Bruck†
Slides Abstract
Session VI: Persistence
Price Center Ballroom West

Chair: Nisha Talagala

Transaction Logging Unleashed with NVRAM
University of Toronto
Tianzheng Wang, Ryan Johnson
Slides Abstract
A Reliable and Highly-Available Non-Volatile Memory System
UC San Diego
Yiying Zhang, Jian Yang, Amirsaman Memaripour, Steven Swanson
Slides Abstract
DAPPER: a database-inspired approach to persistent memory
Intel, Germany∗, University of Edinburgh, UK†
Marcelo Cintra∗, Andreas Chatzistergiou†, Arpit Joshi†, Vijay Nagarajan†, Stratis D. Viglas†
Slides Abstract
Persistency programming 101
University of Michigan∗, Snowflake Computing†, ARM‡
Aasheesh Kolli∗, Steven Pelley†, Ali Saidi‡, Peter M. Chen∗, Thomas F. Wenisch∗
Slides Abstract

5:15pm - 6:30pm
Travel to Banquet

6:30pm - 9:00pm
Banquet
Mister A's, Gaslamp, San Diego


Tuesday, March 3

7:45am - 9:00am
Continental Breakfast
Price Center Ballroom East

9:00am - 10:00am
Keynote
Price Center Ballroom East

In a World with Persistent Memory...
Andy Rudoff
Principal Engineer, Intel Corporation
Slides

10:00am - 10:40am
Break

10:40am - 12:00pm
Session VII: NVM Potpourri
Price Center Ballroom East

Chair: Jishen Zhao

Block Device Driver Design for Fast NVM Class Devices
HGST San Jose Research Center
Damien Le Moal, Dejan Vucinic, Filip Blagojevic, Cyril Guyot, Zvonimir Z. Bandic
Slides Abstract
Leveraging Nonvolatile Memory in High-Level Synthesis for Accelerator-rich Architecture
UCSB∗, Tsinghua University†, UCLA‡, Peking University◊
Shuangchen Li∗, Ang Li†, Yuan Zhe†, Peng Li‡, Guanyu Sun◊, Yongpan Liu†, Yuan Xie∗
Slides Abstract
Zero-Overhead NVM Crash Resilience
Hewlett Packard Labs
Faisal Nawab, Dhruva Charkrabarti, Terence P. Kelly, Charles B. Morrey III Abstract
The Core-Awareness Principle Designing Faster Garbage Collectors For Hybrid Memories
Princeton University
Ravi Tandon, Andrew Appel, Vivek Pai
Slides Abstract
Session VIII: Error reduction techniques
Price Center Ballroom West

Chair: Shiva Planjery

Programming Initial Step Only: A New Approach to Reducing MLC Flash Memory Retention Errors
San Diego State University∗, Seagate Technology†
Wei Wang∗, Tao Xie∗, Antoine Khoueir†, Youngpil Kim†
Slides Abstract
DSP Techniques to Minimize the Bit Error Rate of Flash Memory Signals
Intel Corporation
Ravi Motwani
Slides
Flash Memory Denoising
Samsung
Amit Berman
Implementing Rank Modulation
California Institute of Technology∗, Intellectual Ventures†, Binghamton University‡, Texas A&M University◊
Yue Li∗, Yanjun Ma†, Eyal En Gad∗, Mina Kim‡, Anxiao (Andrew) Jiang◊, Jehoshua Bruck∗
Slides Abstract

12:00pm - 1:20pm
Lunch/Poster Session
Price Center Ballroom B

1:20pm - 3:00pm
Session IX: Error-correcting codes for NVMs
Price Center Ballroom East

Chair: Andrew Jiang

Optimized Degree Distributions for Binary and Non-Binary LDPC Codes in Flash Memory
UCLA
Kasra Vakilinia, Dariush Divsalar, Richard D. Wesel
Slides Abstract
Half-Product Codes for Flash Memory
Texas A&M UniversityDuke University
Santosh Emmadi, Krishna Narayanan, Henry Pfister
A Constraint Scheme for Correcting Massive Asymmetric Magnitude-1 Errors in Multi-Level NVMs
Technion– Israel Institute of TechnologyTechnion – Israel Institute of Technology
Evyatar Hemo, Yuval Cassuto
Slides Abstract
Quasi-Cyclic Non-Binary LDPC Codes for MLC NAND Flash Memory
UCLA
Clayton Schoeny, Behzad Amiri, Ahmed Hareedy, Lara Dolecek
Slides
Efficient FPGA-based Architectures of Finite Alphabet Iterative Decoders for Flash Memories
Codelucida,LLC
Shiva Kumar Planjery, Benedict J. Reynwar, David Declercq, Bane Vasic
Slides
Session X: Applications
Price Center Ballroom West

Chair: Stephen Bates

NVM Compression: Hybrid Flash-Aware Application Level Compression
MariaDB Corporation∗, SanDisk Corporation†, Intern SanDisk Corporation‡
Jan Lindström∗, Dhananjoy Das†, Torben Mathiasen†, Dulcardo Arteaga‡, Nisha Talagala†
Slides Abstract
What can NVMs do for Neuromorphic Computational Systems - Prospects & Challenges
IIT Bombay
Bipin Rajendran
Multi-streaming RocksDB
Samsung Research Center-Xi’an∗, Samsung Electronics Co.†
Fei Yang∗, Kun Dou∗, Siyu Chen∗, Jeong-Uk Kang†, Sangyeun Cho†
Slides Abstract
Developing a Framework for Analyzing Data Movement within a Memory Management Runtime for Data-Intensive Applications
Lawrence Livermore National Laboratory
Brian Van Essen, Ming Jiang, Maya Gokhale
Slides
B+-Tree Algorithm Design for PCM-Based Main Memory
University of California Santa Barbara∗, Pennsylvania State University†
Ping Chi∗, Wang-Chien Lee†, Yuan Xie∗
Slides Abstract

3:00pm - 3:10pm
Closing Remarks
Price Center Ballroom East