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NVMW 2014

Program

The program below is preliminary and may change before the workshop.
A printable version of the program can be found here.

Sunday, March 9

1:00pm - 4:00pm
Tutorial
Price Center Ballroom East

Data Integrity and Reliability in Storage Stacks
Cheng Huang∗, Hao Zhong†
Microsoft Research∗, Fusion-io†
Slides

6:00pm - 9:00pm
Reception
Sheraton Hotel


Monday, March 10

7:45am - 8:45am
Continental Breakfast
Price Center Ballroom East

8:45am - 9:00am
Opening Remarks
Price Center Ballroom East

9:00am - 10:00am
Keynote
Price Center Ballroom East

The Flash Transformed Data Center
John Scaramuzzo
Senior VP, SanDisk Enterprise Storage Solutions
Slides

10:00am - 10:45am
Break

10:45am - 12:05pm
Session I: System Architectures for Flash
Price Center Ballroom East

Chair: Yitzhak (Tsahi) Birk

High Performance Hardware-Accelerated Flash Key-Value Store
Corporate R&D Center, Toshiba Corporation∗, Electrical Engineering Department, Stanford University†
Shingo Tanaka∗, Christos Kozyrakis†
Slides
Extending Main Memory with Flash-the Optimized SWAP Approach
Memory Solutions Lab, Memory Business, Samsung Electronics
Jihyung Park, Hyuck Han, Sangyeun Cho
Slides Abstract
Controlling Program Parameters to Increase NAND Flash Life for SSD Applications
Seagate Technology
Caitlin Race, Young Pil Kim, Rod Bowman
Slides Abstract
Software-Defined Solid State Disks
UCSD
Sudharsan Seshadri, Sundaram Bhaskaran, Arup De, Yanqin Jin, Robert Liu, Trevor Bunker, Steven Swanson
Slides

12:05pm - 1:45pm
Lunch/Poster Session
Price Center Ballroom B

1:45pm - 3:05pm
Session II: Coding for Enhanced Endurance
Price Center Ballroom East

Chair: Eitan Yaakobi

Coset Coding to Extend the Lifetime of Non-Volatile Memory
Duke University
Adam N. Jacobvitz, Robert Calderbank, Daniel J. Sorin
Slides Abstract
Joint Rewriting and Error Correction in WOM
Texas A&M University∗, Texas A&M University and California Institute of Technology†, California Institute of Technology‡, University at Buffalo, The State University of New York◊
Anxiao (Andrew) Jiang∗, Yue Li†, Eyal En Gad‡, Michael Langberg◊, Jehoshua Bruck‡
Slides Abstract
Write-Amplification Reduction Through Multi-Write Codes in Flash Storage
Technion– Israel Institute of Technology∗, Technion – Israel Institute of Technology†
Saher Odeh∗, Yuval Cassuto†
Slides Abstract
Compression Architecture for Bit-write Reduction in Non-volatile Memory Technologies
University of Pittsburgh
David Dgien, Nathan A. Hunter, Jiayin Li, Kartik Mohonram
Slides
Session III: Devices
Price Center Ballroom A

Chair: Ken Lee

Toward High-density STT-MRAM for Embedded Memory
LEAP
Toshihiro Sugii
Design of Heterojunction Oxide Stack for 3D RRAM Cross-Point Array
Arizona State University
Pai-Yu Chen, Shimeng Yu
Slides Abstract
Memory Intensive Computing
Technion∗, University of Rochester†
Shahar Kvatinsky∗, Eby G. Friedman†, Avinoam Kolodny∗, Uri C. Weiser∗
Slides Abstract
Using analog memory with coupled oscillators for pattern recognition applications
University of Pittsburgh
Steven P. Levitan, Donald M. Chiarulli, Yan Fang
Slides Abstract

3:05pm - 3:25pm
Break

3:25pm - 4:45pm
Session IV: System Architectures for Next-Generation Memories I
Price Center Ballroom East

Chair: Christophe Chevallier

DC Express: low latency protocol for PCM PCIe SSDs
HGST∗, UCSD†
Dejan Vucinic∗, Qingbo Wang∗, Cyril Guyot∗, Robert Mateescu∗, Filip Blagojevic∗, Luiz Franca-Neto∗, Damien Le Moal∗, Trevor Bunker†, Jian Xu†, Steven Swanson†, Zvonimir Bandic∗
Slides Abstract
Software Enabled Wear-Leveling for Hybrid PCM Main Memory on Embedded Systems
Oklahoma State University
Jingtong Hu
Slides Abstract
Writeback-Aware Bandwidth Partitioning for Multi-core Systems with PCM
University of Pittsburgh
Miao Zhou, Yu Du, Bruce Childers, Rami Melhem, Daniel Mosse
High Endurance Low Cost Hybrid Phase-Change Memory (PCM)-NAND Flash Enterprise Class Solid-State Drives
HGST, a Western Digital company
Luiz M Franca-Neto, Robert Mateescu, Cyril Guyot, Qingbo Wang, Dejan Vucinic, Frank Chu, Zvonimir Bandic
Slides
Session V: Coding for Reliability
Price Center Ballroom A

Chair: Xinmiao Zhang

Low-complexity Multi-Bit Iterative Decoders for Non-Volatile Memory Channels
University of Arizona∗, University of Cergy-Pontoise†
Bane Vasic∗, Shiva Planjery†, David Declercq†
Slides Abstract
Coding for Unreliable Memory Cells in TLC Flash
UCLA
Ryan Gabrys, Lara Dolecek
Slides
Efficient Codes for Multilevel Flash Memories
Oregon State University∗, University of Teramo†, Micron Technology‡
B. Bose∗, L. Tallini†, Chandra Varanasi‡
Slides Abstract
The Performance of Polar Codes for Multi-level Flash Memories
Texas A&M and Caltech∗, LSI corporation†, Texas A&M University‡
Yue Li∗, Hakim Alhussien†, Erich F. Haratsch†, Anxiao (Andrew) Jiang‡
Slides Abstract

5:00pm -
Shuttle bus to Sheraton hotel - for those who are not attending the dinner banquet

5:05pm -
Departure to San Diego Museum of Art, one trip only

6:30pm - 9:00pm
Dinner banquet to San Diego Museum of Art


Tuesday, March 11

7:45am - 9:00am
Breakfast
Price Center Ballroom East

9:00am - 10:00am
Keynote
Price Center Ballroom East

NVM and New Storage Design Centers
Kaladhar Voruganti
Senior Technical Director, NetApp Advanced Technology Group
Slides

10:45am - 12:05am
Session VI: System Architectures for Next-Generation Memories II
Price Center Ballroom East

Chair: Zvonimir Bandic

PSS: A prototype storage subsystem based on PCM
IBM Zurich Research Lab∗, University of Patras†
Ioannis Koltsidas∗, Peter Mueller∗, Roman Pletka∗, Thomas Weigold∗, Evangelos Eleftheriou∗, Maria Varsamou†, Athina Ntalla†, Elina Mpougioukou†, Aspasia Palli†, Theodoros Antonakopoulos†
Slides Abstract
Using Managed Runtimes to Tolerate Holes in Wearable Memories
Australian National University∗, Microsoft Research and Univ. Washington†, Microsoft Research‡, EPFL◊
Tiejun Gao∗, Karin Strauss†, Steven Blackburn∗, Kathryn McKinley‡, Doug Burger‡, James Larus◊
Slides Abstract
Comparing Analytical and Simulation Models for Zombie Memories with Permanent Failure
∗, Microsoft Research†, University of Campinas‡
John D. Davis∗, Karin Strauss†, Mark Manasse†, Parikshit Gopalan†, Sergey Yekhanin†, Rodolfo Azevedo‡
Slides Abstract
Exploring Storage Class Memory with Key Value Stores
University of Washington
Katelin Bailey, Peter Hornyack, Luis Ceze, Steven Gribble, Henry Levy
Slides Abstract
Session VII: Applications
Price Center Ballroom A

Chair: Chaitan Baru

Introducing SSDs to the Hadoop MapReduce Framework
Samsung System Architecture Lab∗, Texas A&M Univ.†
Jaehwan Lee∗, Sangwhan Moon†, Yang-Suk Kee∗, Bob Brennan∗
Slides
LightNVM: Lightning Fast Evaluation Platform for Non-Volatile Memories
IT University of Copenhagen∗, Tel Aviv University†, HGST‡
Matias Bjorling∗, Jesper Madsen∗, Philippe Bonnet∗, Aviad Zuck†, Zvonimir Bandic‡, Qingbo Wang‡
Slides Abstract
High Performance Transaction Processing for NVRAM
University of Michigan
Steven Pelley, Thomas F. Wenisch
Slides Abstract
Making Updates DiskI/O Friendly Using SSDs
IBM T.J.Watson Research Center∗, IBM.T.J.Watson Research Center†, IBM. T.J.Watson Research Center‡
Mohammad Sadoghi∗, Kenneth Ross†, Mustafa Canim‡, Bishwaranjan Bhattacharjee∗
Slides Abstract

12:10pm - 1:00pm
Lunch/Poster Session
Price Center Ballroom B

1:15pm - 2:35pm
Session VIII: Data Encoding and Mapping Techniques
Price Center Ballroom East

Chair: Rob Calderbank

Constrained Rank Modulation for Flash Memories
UCLA
Frederic Sala, Lara Dolecek
Slides Abstract
Codes for Fast Writes in Multi-Level NVMs
Technion– Israel Institute of Technology∗, Technion – Israel Institute of Technology†
Evyatar Hemo∗, Yuval Cassuto†
Slides Abstract
Bit Mapping for Balanced PCM Cell Programming
University of Pittsburgh
Yu Du, Miao Zhou, Bruce R. Childers, Daniel Mosse, Rami Melhem
Slides
Highly Reliable Techniques for NAND Flash Memory / ReRAM Hybrid Storage
Chuo University / University of Tokyo∗, Chuo University†
Shuhei Tanakamaru∗, Masafumi Doi†, Ken Takeuchi†

2:40pm - 3:00pm
Break